[PATCH] D22708: TargetOpcodes: Rewrite the documentation for SUBREG_TO_REG

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL278258: TargetOpcodes: Rewrite the documentation for SUBREG_TO_REG (authored by matze).

Changed prior to commit:
  https://reviews.llvm.org/D22708?vs=65189&id=67562#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D22708

Files:
  llvm/trunk/include/llvm/Target/TargetOpcodes.def

Index: llvm/trunk/include/llvm/Target/TargetOpcodes.def
===================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def
@@ -55,10 +55,14 @@
 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
 HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
 
-/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
-/// the first operand is an immediate integer constant. This constant is
-/// often zero, because it is commonly used to assert that the instruction
-/// defining the register implicitly clears the high bits.
+/// SUBREG_TO_REG - Assert the value of bits in a super register.
+/// The result of this instruction is the value of the second operand inserted
+/// into the subregister specified by the third operand. All other bits are
+/// assumed to be equal to the bits in the immediate integer constant in the
+/// first operand. This instruction just communicates information; No code
+/// should be generated.
+/// This is typically used after an instruction where the write to a subregister
+/// implicitly cleared the bits in the super registers.
 HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
 
 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D22708.67562.patch
Type: text/x-patch
Size: 1300 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160810/7eacc600/attachment.bin>