[llvm] r278258 - TargetOpcodes: Rewrite the documentation for SUBREG_TO_REG

[Matthias Braun via llvm-commits]

Author: matze
Date: Wed Aug 10 13:05:50 2016
New Revision: 278258

URL: http://llvm.org/viewvc/llvm-project?rev=278258&view=rev
Log:
TargetOpcodes: Rewrite the documentation for SUBREG_TO_REG

Differential Revision: https://reviews.llvm.org/D22708

Modified:
    llvm/trunk/include/llvm/Target/TargetOpcodes.def

Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=278258&r1=278257&r2=278258&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Wed Aug 10 13:05:50 2016
@@ -55,10 +55,14 @@ HANDLE_TARGET_OPCODE(INSERT_SUBREG)
 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
 HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
 
-/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
-/// the first operand is an immediate integer constant. This constant is
-/// often zero, because it is commonly used to assert that the instruction
-/// defining the register implicitly clears the high bits.
+/// SUBREG_TO_REG - Assert the value of bits in a super register.
+/// The result of this instruction is the value of the second operand inserted
+/// into the subregister specified by the third operand. All other bits are
+/// assumed to be equal to the bits in the immediate integer constant in the
+/// first operand. This instruction just communicates information; No code
+/// should be generated.
+/// This is typically used after an instruction where the write to a subregister
+/// implicitly cleared the bits in the super registers.
 HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
 
 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain