[llvm] r278252 - [Hexagon] Add extra patterns for single-precision min/max instructions

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Aug 10 12:56:24 2016
New Revision: 278252

URL: http://llvm.org/viewvc/llvm-project?rev=278252&view=rev
Log:
[Hexagon] Add extra patterns for single-precision min/max instructions

Added:
    llvm/trunk/test/CodeGen/Hexagon/sf-min-max.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td?rev=278252&r1=278251&r2=278252&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td Wed Aug 10 12:56:24 2016
@@ -134,13 +134,13 @@ let isCommutable = 1 in {
 
 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
 
-def: Pat<(f32 (fadd F32:$src1, F32:$src2)),
+def: Pat<(fadd F32:$src1, F32:$src2),
          (F2_sfadd F32:$src1, F32:$src2)>;
 
-def: Pat<(f32 (fsub F32:$src1, F32:$src2)),
+def: Pat<(fsub F32:$src1, F32:$src2),
          (F2_sfsub F32:$src1, F32:$src2)>;
 
-def: Pat<(f32 (fmul F32:$src1, F32:$src2)),
+def: Pat<(fmul F32:$src1, F32:$src2),
          (F2_sfmpy F32:$src1, F32:$src2)>;
 
 let Itinerary = M_tc_3x_SLOT23 in {
@@ -149,21 +149,21 @@ let Itinerary = M_tc_3x_SLOT23 in {
 }
 
 let AddedComplexity = 100, Predicates = [HasV5T] in {
-  def: Pat<(f32 (select (i1 (setolt F32:$src1, F32:$src2)),
-                        F32:$src1, F32:$src2)),
-           (F2_sfmin F32:$src1, F32:$src2)>;
-
-  def: Pat<(f32 (select (i1 (setogt F32:$src1, F32:$src2)),
-                        F32:$src2, F32:$src1)),
-           (F2_sfmin F32:$src1, F32:$src2)>;
-
-  def: Pat<(f32 (select (i1 (setogt F32:$src1, F32:$src2)),
-                        F32:$src1, F32:$src2)),
-           (F2_sfmax F32:$src1, F32:$src2)>;
-
-  def: Pat<(f32 (select (i1 (setolt F32:$src1, F32:$src2)),
-                        F32:$src2, F32:$src1)),
-           (F2_sfmax F32:$src1, F32:$src2)>;
+  class SfSel12<PatFrag Cmp, InstHexagon MI>
+    : Pat<(select (i1 (Cmp F32:$Rs, F32:$Rt)), F32:$Rs, F32:$Rt),
+          (MI F32:$Rs, F32:$Rt)>;
+  class SfSel21<PatFrag Cmp, InstHexagon MI>
+    : Pat<(select (i1 (Cmp F32:$Rs, F32:$Rt)), F32:$Rt, F32:$Rs),
+          (MI F32:$Rs, F32:$Rt)>;
+
+  def: SfSel12<setolt, F2_sfmin>;
+  def: SfSel12<setole, F2_sfmin>;
+  def: SfSel12<setogt, F2_sfmax>;
+  def: SfSel12<setoge, F2_sfmax>;
+  def: SfSel21<setolt, F2_sfmax>;
+  def: SfSel21<setole, F2_sfmax>;
+  def: SfSel21<setogt, F2_sfmin>;
+  def: SfSel21<setoge, F2_sfmin>;
 }
 
 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;

Added: llvm/trunk/test/CodeGen/Hexagon/sf-min-max.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/sf-min-max.ll?rev=278252&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/sf-min-max.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/sf-min-max.ll Wed Aug 10 12:56:24 2016
@@ -0,0 +1,67 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: sf_min_olt:
+; CHECK: sfmin
+define float @sf_min_olt(float %x, float %y) #0 {
+  %t = fcmp olt float %x, %y
+  %u = select i1 %t, float %x, float %y
+  ret float %u
+}
+
+; CHECK-LABEL: sf_min_ole:
+; CHECK: sfmin
+define float @sf_min_ole(float %x, float %y) #0 {
+  %t = fcmp ole float %x, %y
+  %u = select i1 %t, float %x, float %y
+  ret float %u
+}
+
+; CHECK-LABEL: sf_max_ogt:
+; CHECK: sfmax
+define float @sf_max_ogt(float %x, float %y) #0 {
+  %t = fcmp ogt float %x, %y
+  %u = select i1 %t, float %x, float %y
+  ret float %u
+}
+
+; CHECK-LABEL: sf_max_oge:
+; CHECK: sfmax
+define float @sf_max_oge(float %x, float %y) #0 {
+  %t = fcmp oge float %x, %y
+  %u = select i1 %t, float %x, float %y
+  ret float %u
+}
+
+; CHECK-LABEL: sf_max_olt:
+; CHECK: sfmax
+define float @sf_max_olt(float %x, float %y) #0 {
+  %t = fcmp olt float %x, %y
+  %u = select i1 %t, float %y, float %x
+  ret float %u
+}
+
+; CHECK-LABEL: sf_max_ole:
+; CHECK: sfmax
+define float @sf_max_ole(float %x, float %y) #0 {
+  %t = fcmp ole float %x, %y
+  %u = select i1 %t, float %y, float %x
+  ret float %u
+}
+
+; CHECK-LABEL: sf_min_ogt:
+; CHECK: sfmin
+define float @sf_min_ogt(float %x, float %y) #0 {
+  %t = fcmp ogt float %x, %y
+  %u = select i1 %t, float %y, float %x
+  ret float %u
+}
+
+; CHECK-LABEL: sf_min_oge:
+; CHECK: sfmin
+define float @sf_min_oge(float %x, float %y) #0 {
+  %t = fcmp oge float %x, %y
+  %u = select i1 %t, float %y, float %x
+  ret float %u
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }