[llvm] r278236 - [Hexagon] Remove unneeded/unused ISD opcodes ARGEXTEND and FCONST32
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 10 09:20:33 PDT 2016
Author: kparzysz
Date: Wed Aug 10 11:20:33 2016
New Revision: 278236
URL: http://llvm.org/viewvc/llvm-project?rev=278236&view=rev
Log:
[Hexagon] Remove unneeded/unused ISD opcodes ARGEXTEND and FCONST32
Modified:
llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
Modified: llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp?rev=278236&r1=278235&r2=278236&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp Wed Aug 10 11:20:33 2016
@@ -1660,7 +1660,6 @@ int HexagonAsmParser::processInstruction
case Hexagon::CONST32:
case Hexagon::CONST32_Float_Real:
case Hexagon::CONST32_Int_Real:
- case Hexagon::FCONST32_nsdata:
is32bit = true;
// Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
case Hexagon::CONST64_Float_Real:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=278236&r1=278235&r2=278236&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Wed Aug 10 11:20:33 2016
@@ -305,7 +305,6 @@ void HexagonAsmPrinter::HexagonProcessIn
case Hexagon::CONST32:
case Hexagon::CONST32_Float_Real:
case Hexagon::CONST32_Int_Real:
- case Hexagon::FCONST32_nsdata:
if (!OutStreamer->hasRawTextSupport()) {
MCOperand &Imm = MappedInst.getOperand(1);
MCSectionSubPair Current = OutStreamer->getCurrentSection();
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=278236&r1=278235&r2=278236&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Aug 10 11:20:33 2016
@@ -2215,7 +2215,6 @@ HexagonTargetLowering::HexagonTargetLowe
const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((HexagonISD::NodeType)Opcode) {
case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
- case HexagonISD::ARGEXTEND: return "HexagonISD::ARGEXTEND";
case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
@@ -2230,7 +2229,6 @@ const char* HexagonTargetLowering::getTa
case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
- case HexagonISD::FCONST32: return "HexagonISD::FCONST32";
case HexagonISD::INSERT: return "HexagonISD::INSERT";
case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
case HexagonISD::JT: return "HexagonISD::JT";
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=278236&r1=278235&r2=278236&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Wed Aug 10 11:20:33 2016
@@ -31,9 +31,7 @@ bool isPositiveHalfWord(SDNode *N);
CONST32 = OP_BEGIN,
CONST32_GP, // For marking data present in GP.
- FCONST32,
ALLOCA,
- ARGEXTEND,
AT_GOT, // Index in GOT.
AT_PCREL, // Offset relative to PC.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=278236&r1=278235&r2=278236&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Aug 10 11:20:33 2016
@@ -5127,18 +5127,6 @@ def ALLOCA: ALU32Inst<(outs IntRegs:$Rd)
let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
def ALIGNA : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
-def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
-def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
-let isCodeGenOnly = 1 in
-def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
- "$dst = $src1",
- [(set (i32 IntRegs:$dst),
- (Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
-
-let AddedComplexity = 100 in
-def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
- (i32 IntRegs:$src1)>;
-
def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td?rev=278236&r1=278235&r2=278236&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td Wed Aug 10 11:20:33 2016
@@ -67,17 +67,6 @@ def C4_fastcorner9_not : T_LOGICAL_2OP<"
let Inst{20,13,7,4} = 0b1111;
}
-def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>,
- SDTCisPtrTy<1>]>;
-def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
-
-let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
-def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
- "$dst = CONST32(#$global)",
- [(set F32:$dst,
- (HexagonFCONST32 tglobaladdr:$global))]>,
- Requires<[HasV5T]>;
-
let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
"$dst = CONST64(#$src1)",
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