[llvm] r278086 - X86InstrInfo: Update liveness in classifyLea()
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 9 08:56:09 PDT 2016
Thanks! I've merged this to 3.9 in r278128.
- Hans
On Mon, Aug 8, 2016 at 6:47 PM, Matthias Braun via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: matze
> Date: Mon Aug 8 20:47:26 2016
> New Revision: 278086
>
> URL: http://llvm.org/viewvc/llvm-project?rev=278086&view=rev
> Log:
> X86InstrInfo: Update liveness in classifyLea()
>
> We need to update liveness information when we create COPYs in
> classifyLea().
>
> This fixes http://llvm.org/28301
>
> Modified:
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> llvm/trunk/lib/Target/X86/X86InstrInfo.h
> llvm/trunk/test/CodeGen/X86/twoaddr-lea.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=278086&r1=278085&r2=278086&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Aug 8 20:47:26 2016
> @@ -2909,7 +2909,8 @@ inline static bool isTruncatedShiftCount
> bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
> unsigned Opc, bool AllowSP, unsigned &NewSrc,
> bool &isKill, bool &isUndef,
> - MachineOperand &ImplicitOp) const {
> + MachineOperand &ImplicitOp,
> + LiveVariables *LV) const {
> MachineFunction &MF = *MI.getParent()->getParent();
> const TargetRegisterClass *RC;
> if (AllowSP) {
> @@ -2947,13 +2948,17 @@ bool X86InstrInfo::classifyLEAReg(Machin
> // Virtual register of the wrong class, we have to create a temporary 64-bit
> // vreg to feed into the LEA.
> NewSrc = MF.getRegInfo().createVirtualRegister(RC);
> - BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
> + MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
> + get(TargetOpcode::COPY))
> .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
> .addOperand(Src);
>
> // Which is obviously going to be dead after we're done with it.
> isKill = true;
> isUndef = false;
> +
> + if (LV)
> + LV->replaceKillInstruction(SrcReg, MI, *Copy);
> }
>
> // We've set all the parameters without issue.
> @@ -3132,7 +3137,7 @@ X86InstrInfo::convertToThreeAddress(Mach
> unsigned SrcReg;
> MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
> if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
> - SrcReg, isKill, isUndef, ImplicitOp))
> + SrcReg, isKill, isUndef, ImplicitOp, LV))
> return nullptr;
>
> MachineInstrBuilder MIB =
> @@ -3175,7 +3180,7 @@ X86InstrInfo::convertToThreeAddress(Mach
> unsigned SrcReg;
> MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
> if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
> - SrcReg, isKill, isUndef, ImplicitOp))
> + SrcReg, isKill, isUndef, ImplicitOp, LV))
> return nullptr;
>
> MachineInstrBuilder MIB =
> @@ -3209,7 +3214,7 @@ X86InstrInfo::convertToThreeAddress(Mach
> unsigned SrcReg;
> MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
> if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
> - SrcReg, isKill, isUndef, ImplicitOp))
> + SrcReg, isKill, isUndef, ImplicitOp, LV))
> return nullptr;
>
> MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
> @@ -3248,7 +3253,7 @@ X86InstrInfo::convertToThreeAddress(Mach
> unsigned SrcReg;
> MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
> if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
> - SrcReg, isKill, isUndef, ImplicitOp))
> + SrcReg, isKill, isUndef, ImplicitOp, LV))
> return nullptr;
>
> const MachineOperand &Src2 = MI.getOperand(2);
> @@ -3256,7 +3261,7 @@ X86InstrInfo::convertToThreeAddress(Mach
> unsigned SrcReg2;
> MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
> if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
> - SrcReg2, isKill2, isUndef2, ImplicitOp2))
> + SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
> return nullptr;
>
> MachineInstrBuilder MIB =
> @@ -3319,7 +3324,7 @@ X86InstrInfo::convertToThreeAddress(Mach
> unsigned SrcReg;
> MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
> if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
> - SrcReg, isKill, isUndef, ImplicitOp))
> + SrcReg, isKill, isUndef, ImplicitOp, LV))
> return nullptr;
>
> MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=278086&r1=278085&r2=278086&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Aug 8 20:47:26 2016
> @@ -230,7 +230,7 @@ public:
> bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
> unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
> bool &isKill, bool &isUndef,
> - MachineOperand &ImplicitOp) const;
> + MachineOperand &ImplicitOp, LiveVariables *LV) const;
>
> /// convertToThreeAddress - This method must be implemented by targets that
> /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
>
> Modified: llvm/trunk/test/CodeGen/X86/twoaddr-lea.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/twoaddr-lea.ll?rev=278086&r1=278085&r2=278086&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/twoaddr-lea.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/twoaddr-lea.ll Mon Aug 8 20:47:26 2016
> @@ -44,3 +44,60 @@ entry:
> %0 = shl i64 %x, 1
> ret i64 %0
> }
> +
> + at global = external global i32, align 4
> + at global2 = external global i64, align 8
> +
> +; Test that liveness is properly updated and we do not encounter the
> +; assert/crash from http://llvm.org/PR28301
> +; CHECK-LABEL: ham
> +define void @ham() {
> +bb:
> + br label %bb1
> +
> +bb1:
> + %tmp = phi i64 [ %tmp40, %bb9 ], [ 0, %bb ]
> + %tmp2 = phi i32 [ %tmp39, %bb9 ], [ 0, %bb ]
> + %tmp3 = icmp sgt i32 undef, 10
> + br i1 %tmp3, label %bb2, label %bb3
> +
> +bb2:
> + %tmp6 = load i32, i32* @global, align 4
> + %tmp8 = add nsw i32 %tmp6, %tmp2
> + %tmp9 = sext i32 %tmp8 to i64
> + br label %bb6
> +
> +bb3:
> +; CHECK: subl %e[[REG0:[a-z0-9]+]],
> +; CHECK: leaq 4({{%[a-z0-9]+}}), %r[[REG0]]
> + %tmp14 = phi i64 [ %tmp15, %bb5 ], [ 0, %bb1 ]
> + %tmp15 = add nuw i64 %tmp14, 4
> + %tmp16 = trunc i64 %tmp14 to i32
> + %tmp17 = sub i32 %tmp2, %tmp16
> + br label %bb4
> +
> +bb4:
> + %tmp20 = phi i64 [ %tmp14, %bb3 ], [ %tmp34, %bb5 ]
> + %tmp28 = icmp eq i32 %tmp17, 0
> + br i1 %tmp28, label %bb5, label %bb8
> +
> +bb5:
> + %tmp34 = add nuw nsw i64 %tmp20, 1
> + %tmp35 = icmp slt i64 %tmp34, %tmp15
> + br i1 %tmp35, label %bb4, label %bb3
> +
> +bb6:
> + store volatile i64 %tmp, i64* @global2, align 8
> + store volatile i64 %tmp9, i64* @global2, align 8
> + store volatile i32 %tmp6, i32* @global, align 4
> + %tmp45 = icmp slt i32 undef, undef
> + br i1 %tmp45, label %bb6, label %bb9
> +
> +bb8:
> + unreachable
> +
> +bb9:
> + %tmp39 = add nuw nsw i32 %tmp2, 4
> + %tmp40 = add nuw i64 %tmp, 4
> + br label %bb1
> +}
>
>
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