[PATCH] D23269: AArch64: Move remaining target specific BranchRelaxation bits to TII

[Tim Northover via llvm-commits]

t.p.northover added a subscriber: t.p.northover.

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Comment at: lib/Target/AArch64/AArch64InstrInfo.cpp:114-115
@@ -113,2 +113,4 @@
     llvm_unreachable("unexpected opcode!");
+  case AArch64::B:
+    return 64;
   case AArch64::TBNZW:
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This doesn't look right to me. I see that it's coming from a "return -1" but unconditional branches don't have unlimited range. They've got 26-bit signed range.

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Comment at: lib/Target/AArch64/AArch64InstrInfo.h:172-175
@@ -149,1 +171,6 @@
+  /// \returns The number of bytes added to the block.
+  unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
+                                     MachineBasicBlock &DestBB,
+                                     const DebugLoc &DL,
+                                     int64_t BrOffset = 0) const;
 
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Could these APIs be expressed in terms of InsertBranch? At the moment it seems like we're crafting a parallel set of special-purpose branch-mangling functions but instead we could add something like

    SmallVectorImpl<MachineOperand> getUnconditionalCond();
    SmallVectorImpl<MachineOperand> getInvertedCond(SmallVectorImpl<MachineOperand> &Cond);

(feel free to bikeshed the interface, I'm not attached) and then these 3 become fairly simple wrappers around the existing functionality.


https://reviews.llvm.org/D23269