[llvm] r277447 - [GlobalISel] Don't RegBankSelect target-specific instructions.

[Quentin Colombet via llvm-commits]

> On Aug 2, 2016, at 4:41 AM, Ahmed Bougacha via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: ab
> Date: Tue Aug  2 06:41:16 2016
> New Revision: 277447
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=277447&view=rev
> Log:
> [GlobalISel] Don't RegBankSelect target-specific instructions.
> 
> They don't have types and should be using register classes.
> 
> Modified:
>    llvm/trunk/include/llvm/Target/TargetOpcodes.h
>    llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
> 
> Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=277447&r1=277446&r2=277447&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetOpcodes.h Tue Aug  2 06:41:16 2016
> @@ -32,6 +32,11 @@ static inline bool isPreISelGenericOpcod
>   return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START &&
>          Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
> }
> +
> +/// Check whether the given Opcode is a target-specific opcode.
> +static inline bool isTargetSpecificOpcode(unsigned Opcode) {
> +  return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
> +}
> } // end namespace llvm
> 
> #endif
> 
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp?rev=277447&r1=277446&r2=277447&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp Tue Aug  2 06:41:16 2016
> @@ -554,7 +554,13 @@ bool RegBankSelect::runOnMachineFunction
>          MII != End;) {
>       // MI might be invalidated by the assignment, so move the
>       // iterator before hand.
> -      assignInstr(*MII++);
> +      MachineInstr &MI = *MII++;
> +
> +      // Ignore target-specific instructions: they should use proper regclasses.
> +      if (isTargetSpecificOpcode(MI.getOpcode()))
> +        continue;
> +
> +      assignInstr(MI);

Being able to remap target specific instructions was actually a feature. What problems were you seeing? 

>     }
>   }
>   OptMode = SaveOptMode;
> 
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=277447&r1=277446&r2=277447&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Tue Aug  2 06:41:16 2016
> @@ -54,6 +54,8 @@
>   entry:
>     ret void
>   }
> +
> +  define void @ignoreTargetSpecificInst() { ret void }
> ...
> 
> ---
> @@ -327,3 +329,28 @@ body: |
>     %1(64) = COPY %x1
>     %2(64) = G_OR <2 x s32> %0, %1
> ...
> +
> +---
> +# CHECK-LABEL: name: ignoreTargetSpecificInst
> +name:            ignoreTargetSpecificInst
> +isSSA:           true
> +# CHECK:      registers:
> +# CHECK-NEXT:  - { id: 0, class: gpr64 }
> +# CHECK-NEXT:  - { id: 1, class: gpr64 }
> +registers:
> +  - { id: 0, class: gpr64 }
> +  - { id: 1, class: gpr64 }
> +body: |
> +  bb.0:
> +    liveins: %x0
> +
> +    ; CHECK: %0 = COPY %x0
> +    ; CHECK-NEXT: %1 = ADDXrr %0, %0
> +    ; CHECK-NEXT: %x0 = COPY %1
> +    ; CHECK-NEXT: RET_ReallyLR implicit %x0
> +
> +    %0 = COPY %x0
> +    %1 = ADDXrr %0, %0
> +    %x0 = COPY %1
> +    RET_ReallyLR implicit %x0
> +...
> 
> 
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