[PATCH] D23172: Treat aliased registers as live in if-conversion

[Krzysztof Parzyszek via llvm-commits]

kparzysz created this revision.
kparzysz added reviewers: qcolombet, jonpa.
kparzysz added a subscriber: llvm-commits.
kparzysz set the repository for this revision to rL LLVM.

When the if-converter adds implicit uses, it compares the list of clobbers by the predicated instruction with the list of live registers.  These two can be disjoint in terms of actual contents, but contain registers aliased to a register from the other list.

Repository:
  rL LLVM

https://reviews.llvm.org/D23172

Files:
  lib/CodeGen/IfConversion.cpp
  test/CodeGen/Hexagon/ifcvt-impuse.ll

Index: test/CodeGen/Hexagon/ifcvt-impuse.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Hexagon/ifcvt-impuse.ll
@@ -0,0 +1,42 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: r17:16 = combine(r0, r1)
+
+; After if-conversion, the early exit is predicated, together with the
+; restore of d8:
+;   if (!p0.new) r17:16 = memd(r29 + #0)
+;
+; If the if-converter does not add implicit uses to this predicated load,
+; the copy-in from d0 to d8 will become dead. The if-converter can miss
+; this, because the live-in information contains r16 and r17, but not d8
+; explicitly.
+
+target triple = "hexagon"
+
+define double @fred(i32 %n, double* nocapture readonly %a) local_unnamed_addr #0 {
+entry:
+  %cmp5 = icmp slt i32 %n, 1
+  br i1 %cmp5, label %for.end, label %for.body.preheader
+
+for.body.preheader:                               ; preds = %entry
+  br label %for.body
+
+for.body:                                         ; preds = %for.body.preheader, %for.body
+  %sum.07 = phi double [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]
+  %i.06 = phi i32 [ %inc, %for.body ], [ 1, %for.body.preheader ]
+  %sub = add nsw i32 %i.06, -1
+  %arrayidx = getelementptr inbounds double, double* %a, i32 %sub
+  %0 = load double, double* %arrayidx, align 8
+  %add = fadd double %sum.07, %0
+  %inc = add nuw nsw i32 %i.06, 1
+  %exitcond = icmp eq i32 %i.06, %n
+  br i1 %exitcond, label %for.end.loopexit, label %for.body
+
+for.end.loopexit:                                 ; preds = %for.body
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %entry
+  %sum.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %add, %for.end.loopexit ]
+  ret double %sum.0.lcssa
+}
+
+attributes #0 = { nounwind optsize readonly "target-cpu"="hexagonv55" }
Index: lib/CodeGen/IfConversion.cpp
===================================================================
--- lib/CodeGen/IfConversion.cpp
+++ lib/CodeGen/IfConversion.cpp
@@ -1072,6 +1072,7 @@
 /// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
 /// values defined in MI which are also live/used by MI.
 static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
+dbgs() << __func__ << "  Redefs:" << Redefs << "  MI:" << MI;
   const TargetRegisterInfo *TRI = MI.getParent()->getParent()
     ->getSubtarget().getRegisterInfo();
 
@@ -1081,7 +1082,8 @@
   SparseSet<unsigned> LiveBeforeMI;
   LiveBeforeMI.setUniverse(TRI->getNumRegs());
   for (auto &Reg : Redefs)
-    LiveBeforeMI.insert(Reg);
+    for (MCRegAliasIterator A(Reg, TRI, true); A.isValid(); ++A)
+      LiveBeforeMI.insert(*A);
 
   SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Clobbers;
   Redefs.stepForward(MI, Clobbers);


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