[llvm] r277727 - [Hexagon] Clear kill flags from modified registers in peephole optimizer

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Aug  4 09:17:16 2016
New Revision: 277727

URL: http://llvm.org/viewvc/llvm-project?rev=277727&view=rev
Log:
[Hexagon] Clear kill flags from modified registers in peephole optimizer

Added:
    llvm/trunk/test/CodeGen/Hexagon/peephole-kill-flags.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp?rev=277727&r1=277726&r2=277727&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp Thu Aug  4 09:17:16 2016
@@ -250,6 +250,7 @@ bool HexagonPeephole::runOnMachineFuncti
               if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
                 // Change the 1st operand and, flip the opcode.
                 MI.getOperand(0).setReg(PeepholeSrc);
+                MRI->clearKillFlags(PeepholeSrc);
                 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
                 MI.setDesc(QII->get(NewOp));
                 Done = true;
@@ -280,6 +281,7 @@ bool HexagonPeephole::runOnMachineFuncti
             unsigned PSrc = MI.getOperand(PR).getReg();
             if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
               MI.getOperand(PR).setReg(POrig);
+              MRI->clearKillFlags(POrig);
               MI.setDesc(QII->get(NewOp));
               // Swap operands S1 and S2.
               MachineOperand Op1 = MI.getOperand(S1);
@@ -304,6 +306,7 @@ void HexagonPeephole::ChangeOpInto(Machi
       if (Src.isReg()) {
         Dst.setReg(Src.getReg());
         Dst.setSubReg(Src.getSubReg());
+        MRI->clearKillFlags(Src.getReg());
       } else if (Src.isImm()) {
         Dst.ChangeToImmediate(Src.getImm());
       } else {
@@ -316,7 +319,7 @@ void HexagonPeephole::ChangeOpInto(Machi
         Dst.setImm(Src.getImm());
       } else if (Src.isReg()) {
         Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
-                             Src.isKill(), Src.isDead(), Src.isUndef(),
+                             false, Src.isDead(), Src.isUndef(),
                              Src.isDebug());
         Dst.setSubReg(Src.getSubReg());
       } else {

Added: llvm/trunk/test/CodeGen/Hexagon/peephole-kill-flags.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/peephole-kill-flags.ll?rev=277727&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/peephole-kill-flags.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/peephole-kill-flags.ll Thu Aug  4 09:17:16 2016
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
+; CHECK: memw
+
+; Check that the testcase compiles without errors.
+
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define void @fred() #0 {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %entry
+  %0 = load i32, i32* undef, align 4
+  %mul = mul nsw i32 2, %0
+  %cmp = icmp slt i32 undef, %mul
+  br i1 %cmp, label %for.body, label %for.end13
+
+for.body:                                         ; preds = %for.cond
+  unreachable
+
+for.end13:                                        ; preds = %for.cond
+  ret void
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
+