[PATCH] D23163: [AVX512][FastISel] Do not use K registers in TEST instructions

[Guy Blank via llvm-commits]

guyblank created this revision.
guyblank added reviewers: delena, igorb.
guyblank added a subscriber: llvm-commits.

since i1 is legal in AVX512, i1 values weren't promoted to i8, instead K registers were allocated.
this causes an issue when they are passed to a TEST instruction, which is illegal.

Solves Bug 28661

while this patch solves this specific issue, what I would really want to do is make the isel choose GPRs for these i1 values.



https://reviews.llvm.org/D23163

Files:
  lib/Target/X86/X86FastISel.cpp

Index: lib/Target/X86/X86FastISel.cpp
===================================================================
--- lib/Target/X86/X86FastISel.cpp
+++ lib/Target/X86/X86FastISel.cpp
@@ -1651,6 +1651,7 @@
       if (TestOpc) {
         unsigned OpReg = getRegForValue(TI->getOperand(0));
         if (OpReg == 0) return false;
+
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
           .addReg(OpReg).addImm(1);
 
@@ -1688,6 +1689,15 @@
   unsigned OpReg = getRegForValue(BI->getCondition());
   if (OpReg == 0) return false;
 
+  // In case OpReg is a K register, move it to a GPR to be able to use the
+  // TEST instruction.
+  if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) {
+    unsigned tmp = OpReg;
+    OpReg = createResultReg(&X86::GR8RegClass);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+            TII.get(TargetOpcode::COPY), OpReg)
+        .addReg(tmp);
+  }
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
     .addReg(OpReg).addImm(1);
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_1))
@@ -2023,6 +2033,16 @@
       return false;
     bool CondIsKill = hasTrivialKill(Cond);
 
+    // In case CondReg is a K register, move it to a GPR to be able to use the
+    // TEST instruction.
+    if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
+      unsigned tmp = CondReg;
+      CondReg = createResultReg(&X86::GR8RegClass);
+      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+              TII.get(TargetOpcode::COPY), CondReg)
+          .addReg(tmp, getKillRegState(CondIsKill));
+    }
+
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
       .addReg(CondReg, getKillRegState(CondIsKill)).addImm(1);
   }
@@ -2195,6 +2215,17 @@
     if (CondReg == 0)
       return false;
     bool CondIsKill = hasTrivialKill(Cond);
+
+    // In case CondReg is a K register, move it to a GPR to be able to use the
+    // TEST instruction.
+    if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) {
+      unsigned tmp = CondReg;
+      CondReg = createResultReg(&X86::GR8RegClass);
+      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+              TII.get(TargetOpcode::COPY), CondReg)
+          .addReg(tmp, getKillRegState(CondIsKill));
+    }
+
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
       .addReg(CondReg, getKillRegState(CondIsKill)).addImm(1);
   }


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