[PATCH] D23155: Power9 - Part-word VSX integer scalar loads/stores and sign extend instructions

[Nemanja Ivanovic via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: hfinkel, kbarton, amehsan, cycheng, wschmidt.
nemanjai added subscribers: echristo, llvm-commits.
nemanjai set the repository for this revision to rL LLVM.
Herald added subscribers: nemanjai, qcolombet.

This patch uses a portion of https://reviews.llvm.org/D20310 that removes the VSHRC register class. The reason for this is that these instructions have a similar need for the changes to the register classes and the other revision is on hold for now. When this revision is committed, the other one will simply be an addition of the patterns for the instructions.

The new instructions are useful for a few purposes:
- Int to Fp conversions of 1 or 2-byte values loaded from memory
- Building vectors of 1 or 2-byte integers with values loaded from memory
- Storing individual 1 or 2-byte elements from integer vectors

This patch implements all of those uses.

Repository:
  rL LLVM

https://reviews.llvm.org/D23155

Files:
  lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
  lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
  lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  lib/Target/PowerPC/PPCAsmPrinter.cpp
  lib/Target/PowerPC/PPCCallingConv.td
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.h
  lib/Target/PowerPC/PPCInstrAltivec.td
  lib/Target/PowerPC/PPCInstrFormats.td
  lib/Target/PowerPC/PPCInstrInfo.cpp
  lib/Target/PowerPC/PPCInstrInfo.h
  lib/Target/PowerPC/PPCInstrInfo.td
  lib/Target/PowerPC/PPCInstrVSX.td
  lib/Target/PowerPC/PPCMIPeephole.cpp
  lib/Target/PowerPC/PPCRegisterInfo.cpp
  lib/Target/PowerPC/PPCRegisterInfo.td
  lib/Target/PowerPC/PPCVSXCopy.cpp
  test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll
  test/CodeGen/PowerPC/load-v4i8-improved.ll
  test/CodeGen/PowerPC/machine-combiner.ll
  test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
  test/CodeGen/PowerPC/select-i1-vs-i1.ll
  test/CodeGen/PowerPC/sjlj.ll
  test/CodeGen/PowerPC/vsx-args.ll
  test/CodeGen/PowerPC/vsx-infl-copy1.ll
  test/CodeGen/PowerPC/vsx-p8.ll
  test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll
  test/CodeGen/PowerPC/vsx-spill-norwstore.ll
  test/CodeGen/PowerPC/vsx-vec-spill.ll
  test/CodeGen/PowerPC/vsx.ll

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