[llvm] r276624 - [ARM] Enable ISel of SMMLS for ARM and Thumb2
Vedant Kumar via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 2 15:16:27 PDT 2016
Hi Sam,
This commit is breaking our internal ARM test suite.
I've attached a reproducer to this email. If it's not inconvenient for you, it
would really help us out if you could revert this temporarily.
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thanks,
vedant
> On Jul 25, 2016, at 2:20 AM, Sam Parker via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> Author: sam_parker
> Date: Mon Jul 25 04:20:20 2016
> New Revision: 276624
>
> URL: http://llvm.org/viewvc/llvm-project?rev=276624&view=rev
> Log:
> [ARM] Enable ISel of SMMLS for ARM and Thumb2
>
> Use ISelDAGToDAG to recognise the SMMLS instruction pattern.
>
> Differential Revision: https://reviews.llvm.org/D22562
>
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> llvm/trunk/test/CodeGen/ARM/smml.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=276624&r1=276623&r2=276624&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Jul 25 04:20:20 2016
> @@ -3037,6 +3037,36 @@ void ARMDAGToDAGISel::Select(SDNode *N)
> return;
> }
> }
> + case ARMISD::SUBE: {
> + if (!Subtarget->hasV6Ops())
> + break;
> + // Look for a pattern to match SMMLS
> + // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b))))
> + if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
> + N->getOperand(2).getOpcode() != ARMISD::SUBC)
> + break;
> +
> + if (Subtarget->isThumb())
> + assert(Subtarget->hasThumb2() &&
> + "This pattern should not be generated for Thumb");
> +
> + SDValue SmulLoHi = N->getOperand(1);
> + SDValue Subc = N->getOperand(2);
> + auto *Zero = dyn_cast<ConstantSDNode>(Subc.getOperand(0));
> +
> + if (!Zero || Zero->getZExtValue() != 0 ||
> + Subc.getOperand(1) != SmulLoHi.getValue(0) ||
> + N->getOperand(1) != SmulLoHi.getValue(1) ||
> + N->getOperand(2) != Subc.getValue(1))
> + break;
> +
> + unsigned Opc = Subtarget->isThumb2() ? ARM::t2SMMLS : ARM::SMMLS;
> + SDValue Ops[] = { SmulLoHi.getOperand(0), SmulLoHi.getOperand(1),
> + N->getOperand(0), getAL(CurDAG, dl),
> + CurDAG->getRegister(0, MVT::i32) };
> + ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops));
> + return;
> + }
> case ISD::LOAD: {
> if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
> if (tryT2IndexedLoad(N))
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=276624&r1=276623&r2=276624&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jul 25 04:20:20 2016
> @@ -2604,12 +2604,11 @@ class T2FourRegSMMLA<bits<3> op22_20, bi
> let Inst{7-4} = op7_4;
> }
>
> -def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
> +def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla",
> [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
> -def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
> -def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
> - [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
> -def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
> +def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
> +def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>;
> +def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
>
> class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
> list<dag> pattern>
>
> Modified: llvm/trunk/test/CodeGen/ARM/smml.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/smml.ll?rev=276624&r1=276623&r2=276624&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/smml.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/smml.ll Mon Jul 25 04:20:20 2016
> @@ -1,8 +1,20 @@
> -; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
> +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK
> +; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V6
> +; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7
> +; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
> +; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMB
> +; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV6T2
> +; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-THUMBV7
>
> -define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
> +define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
> entry:
> +; CHECK-LABEL: Test0
> ; CHECK-NOT: smmls
> +; CHECK-V6-NOT: smmls
> +; CHECK-V7-NOT: smmls
> +; CHECK_THUMB-NOT: smmls
> +; CHECK-THUMBV6T2-NOT: smmls
> +; CHECK-THUMBV7-NOT: smmls
> %conv4 = zext i32 %a to i64
> %conv1 = sext i32 %b to i64
> %conv2 = sext i32 %c to i64
> @@ -12,3 +24,23 @@ entry:
> %conv3 = trunc i64 %sub to i32
> ret i32 %conv3
> }
> +
> +define i32 @Test1(i32 %a, i32 %b, i32 %c) {
> +;CHECK-LABEL: Test1
> +;CHECK-NOT: smmls
> +;CHECK-THUMB-NOT: smmls
> +;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
> +;CHECK-V7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
> +;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
> +;CHECK-THUMBV7: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
> +entry:
> + %conv = sext i32 %b to i64
> + %conv1 = sext i32 %c to i64
> + %mul = mul nsw i64 %conv1, %conv
> + %conv26 = zext i32 %a to i64
> + %shl = shl nuw i64 %conv26, 32
> + %sub = sub nsw i64 %shl, %mul
> + %shr7 = lshr i64 %sub, 32
> + %conv3 = trunc i64 %shr7 to i32
> + ret i32 %conv3
> +}
>
>
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