[llvm] r277475 - [GlobalISel] Add RegBankSelected MachineFunction property.

[Ahmed Bougacha via llvm-commits]

Author: ab
Date: Tue Aug  2 11:17:10 2016
New Revision: 277475

URL: http://llvm.org/viewvc/llvm-project?rev=277475&view=rev
Log:
[GlobalISel] Add RegBankSelected MachineFunction property.

RegBankSelected: the RegBankSelect pass ran and all generic virtual
registers have been assigned to a register bank.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

Modified:
    llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
    llvm/trunk/include/llvm/CodeGen/MachineFunction.h
    llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
    llvm/trunk/lib/CodeGen/MIRPrinter.cpp
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir

Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=277475&r1=277474&r2=277475&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Tue Aug  2 11:17:10 2016
@@ -386,6 +386,7 @@ struct MachineFunction {
   bool AllVRegsAllocated = false;
   // GISel MachineFunctionProperties.
   bool Legalized = false;
+  bool RegBankSelected = false;
   // Register information
   bool IsSSA = false;
   bool TracksRegLiveness = false;
@@ -411,6 +412,7 @@ template <> struct MappingTraits<Machine
     YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
     YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
     YamlIO.mapOptional("legalized", MF.Legalized);
+    YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
     YamlIO.mapOptional("isSSA", MF.IsSSA);
     YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
     YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=277475&r1=277474&r2=277475&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Aug  2 11:17:10 2016
@@ -122,11 +122,14 @@ public:
   //   - generic and always legal (e.g., COPY)
   //   - target-specific
   //   - legal pre-isel generic instructions.
+  // RegBankSelected: In GlobalISel: the RegBankSelect pass ran and all generic
+  //  virtual registers have been assigned to a register bank.
   enum class Property : unsigned {
     IsSSA,
     TracksLiveness,
     AllVRegsAllocated,
     Legalized,
+    RegBankSelected,
     LastProperty,
   };
 

Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=277475&r1=277474&r2=277475&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Aug  2 11:17:10 2016
@@ -295,6 +295,9 @@ bool MIRParserImpl::initializeMachineFun
 
   if (YamlMF.Legalized)
     MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
+  if (YamlMF.RegBankSelected)
+    MF.getProperties().set(
+        MachineFunctionProperties::Property::RegBankSelected);
 
   PerFunctionMIParsingState PFS(MF, SM, IRSlots);
   if (initializeRegisterInfo(PFS, YamlMF))

Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=277475&r1=277474&r2=277475&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Aug  2 11:17:10 2016
@@ -180,6 +180,8 @@ void MIRPrinter::print(const MachineFunc
 
   YamlMF.Legalized = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Legalized);
+  YamlMF.RegBankSelected = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::RegBankSelected);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=277475&r1=277474&r2=277475&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Aug  2 11:17:10 2016
@@ -79,6 +79,9 @@ void MachineFunctionProperties::print(ra
       case Property::Legalized:
         ROS << (HasProperty ? "" : "not ") << "legalized";
         break;
+      case Property::RegBankSelected:
+        ROS << (HasProperty ? "" : "not ") << "RegBank-selected";
+        break;
       default:
         break;
     }

Modified: llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir?rev=277475&r1=277474&r2=277475&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir Tue Aug  2 11:17:10 2016
@@ -20,6 +20,7 @@
 ---
 # CHECK-LABEL: name: test_defaults
 # CHECK:      legalized: false
+# CHECK-NEXT: regBankSelected: false
 name:            test_defaults
 body: |
   bb.0:
@@ -27,8 +28,10 @@ body: |
 ---
 # CHECK-LABEL: name: test
 # CHECK:      legalized: true
+# CHECK-NEXT: regBankSelected: true
 name: test
 legalized: true
+regBankSelected: true
 body: |
   bb.0:
 ...