[llvm] r277470 - [GlobalISel] Add Legalized MachineFunction property.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 2 08:10:26 PDT 2016
Author: ab
Date: Tue Aug 2 10:10:25 2016
New Revision: 277470
URL: http://llvm.org/viewvc/llvm-project?rev=277470&view=rev
Log:
[GlobalISel] Add Legalized MachineFunction property.
Legalized: The MachineLegalizer ran; all pre-isel generic instructions
have been legalized, i.e., all instructions are now one of:
- generic and always legal (e.g., COPY)
- target-specific
- legal pre-isel generic instructions.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
Added:
llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir
Modified:
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
llvm/trunk/include/llvm/CodeGen/MachineFunction.h
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/lib/CodeGen/MachineFunction.cpp
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=277470&r1=277469&r2=277470&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Tue Aug 2 10:10:25 2016
@@ -384,6 +384,8 @@ struct MachineFunction {
bool HasInlineAsm = false;
// MachineFunctionProperties
bool AllVRegsAllocated = false;
+ // GISel MachineFunctionProperties.
+ bool Legalized = false;
// Register information
bool IsSSA = false;
bool TracksRegLiveness = false;
@@ -408,6 +410,7 @@ template <> struct MappingTraits<Machine
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
+ YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("isSSA", MF.IsSSA);
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=277470&r1=277469&r2=277470&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Aug 2 10:10:25 2016
@@ -117,10 +117,16 @@ public:
// When this property is clear, liveness is no longer reliable.
// AllVRegsAllocated: All virtual registers have been allocated; i.e. all
// register operands are physical registers.
+ // Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic
+ // instructions have been legalized; i.e., all instructions are now one of:
+ // - generic and always legal (e.g., COPY)
+ // - target-specific
+ // - legal pre-isel generic instructions.
enum class Property : unsigned {
IsSSA,
TracksLiveness,
AllVRegsAllocated,
+ Legalized,
LastProperty,
};
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=277470&r1=277469&r2=277470&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Aug 2 10:10:25 2016
@@ -292,6 +292,10 @@ bool MIRParserImpl::initializeMachineFun
MF.setHasInlineAsm(YamlMF.HasInlineAsm);
if (YamlMF.AllVRegsAllocated)
MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);
+
+ if (YamlMF.Legalized)
+ MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
+
PerFunctionMIParsingState PFS(MF, SM, IRSlots);
if (initializeRegisterInfo(PFS, YamlMF))
return true;
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=277470&r1=277469&r2=277470&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Aug 2 10:10:25 2016
@@ -178,6 +178,9 @@ void MIRPrinter::print(const MachineFunc
YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::AllVRegsAllocated);
+ YamlMF.Legalized = MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::Legalized);
+
convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
ModuleSlotTracker MST(MF.getFunction()->getParent());
MST.incorporateFunction(*MF.getFunction());
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=277470&r1=277469&r2=277470&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Aug 2 10:10:25 2016
@@ -76,6 +76,9 @@ void MachineFunctionProperties::print(ra
case Property::AllVRegsAllocated:
ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
break;
+ case Property::Legalized:
+ ROS << (HasProperty ? "" : "not ") << "legalized";
+ break;
default:
break;
}
Added: llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir?rev=277470&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/Generic/global-isel-properties.mir Tue Aug 2 10:10:25 2016
@@ -0,0 +1,34 @@
+# RUN: llc -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses GlobalISel MachineFunction
+# properties correctly.
+# This doesn't require GlobalISel to be built, as the properties are always
+# available in CodeGen.
+
+--- |
+
+ define i32 @test_defaults() {
+ entry:
+ ret i32 0
+ }
+
+ define i32 @test() {
+ start:
+ ret i32 0
+ }
+
+...
+---
+# CHECK-LABEL: name: test_defaults
+# CHECK: legalized: false
+name: test_defaults
+body: |
+ bb.0:
+...
+---
+# CHECK-LABEL: name: test
+# CHECK: legalized: true
+name: test
+legalized: true
+body: |
+ bb.0:
+...
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