[PATCH] D21571: [AArch64] Avoid generating indexed vector instructions for Exynos

[Abderrazek Zaafrani via llvm-commits]

az updated this revision to Diff 66395.
az added a comment.
Herald added subscribers: rengolin, aemerson.

Redone this work as an optimization instead of modifying TableGen. The optimization is based on the latency of instructions and only the latencies for Exynos enable this optimization. This is mainly tested on intrinsic code.


https://reviews.llvm.org/D21571

Files:
  llvm/include/llvm/Target/TargetInstrInfo.h
  llvm/lib/CodeGen/PeepholeOptimizer.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll

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