[llvm] r277358 - Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 1 10:55:48 PDT 2016
Author: kparzysz
Date: Mon Aug 1 12:55:48 2016
New Revision: 277358
URL: http://llvm.org/viewvc/llvm-project?rev=277358&view=rev
Log:
Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFC
There were a few cases introduced with the modulo scheduler.
Modified:
llvm/trunk/include/llvm/Target/TargetInstrInfo.h
llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=277358&r1=277357&r2=277358&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Aug 1 12:55:48 2016
@@ -565,7 +565,7 @@ public:
/// this function when peeling off one or more iterations of a loop. This
/// function assumes the nth iteration is peeled first.
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
- MachineInstr *IndVar, MachineInstr *Cmp,
+ MachineInstr *IndVar, MachineInstr &Cmp,
SmallVectorImpl<MachineOperand> &Cond,
SmallVectorImpl<MachineInstr *> &PrevInsts,
unsigned Iter, unsigned MaxIter) const {
@@ -1033,14 +1033,14 @@ public:
/// Return true if the instruction contains a base register and offset. If
/// true, the function also sets the operand position in the instruction
/// for the base register and offset.
- virtual bool getBaseAndOffsetPosition(const MachineInstr *MI,
+ virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
unsigned &BasePos,
unsigned &OffsetPos) const {
return false;
}
/// If the instruction is an increment of a constant value, return the amount.
- virtual bool getIncrementValue(const MachineInstr *MI, int &Value) const {
+ virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
return false;
}
@@ -1077,7 +1077,7 @@ public:
virtual void getNoopForMachoTarget(MCInst &NopInst) const;
/// Return true for post-incremented instructions.
- virtual bool isPostIncrement(const MachineInstr* MI) const {
+ virtual bool isPostIncrement(const MachineInstr &MI) const {
return false;
}
Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=277358&r1=277357&r2=277358&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Mon Aug 1 12:55:48 2016
@@ -2977,7 +2977,7 @@ void SwingSchedulerDAG::addBranches(MBBV
// Check if the LOOP0 has already been removed. If so, then there is no need
// to reduce the trip count.
if (LC != 0)
- LC = TII->reduceLoopCount(*Prolog, IndVar, Cmp, Cond, PrevInsts, j,
+ LC = TII->reduceLoopCount(*Prolog, IndVar, *Cmp, Cond, PrevInsts, j,
MaxIter);
// Record the value of the first trip count, which is used to determine if
@@ -3035,7 +3035,7 @@ bool SwingSchedulerDAG::computeDelta(Mac
return false;
int D = 0;
- if (!TII->getIncrementValue(BaseDef, D) && D >= 0)
+ if (!TII->getIncrementValue(*BaseDef, D) && D >= 0)
return false;
Delta = D;
@@ -3108,7 +3108,7 @@ MachineInstr *SwingSchedulerDAG::cloneAn
if (It != InstrChanges.end()) {
std::pair<unsigned, int64_t> RegAndOffset = It->second;
unsigned BasePos, OffsetPos;
- if (!TII->getBaseAndOffsetPosition(OldMI, BasePos, OffsetPos))
+ if (!TII->getBaseAndOffsetPosition(*OldMI, BasePos, OffsetPos))
return nullptr;
int64_t NewOffset = OldMI->getOperand(OffsetPos).getImm();
MachineInstr *LoopDef = findDefInLoop(RegAndOffset.first);
@@ -3311,10 +3311,10 @@ bool SwingSchedulerDAG::canUseLastOffset
unsigned &NewBase,
int64_t &Offset) {
// Get the load instruction.
- if (TII->isPostIncrement(MI))
+ if (TII->isPostIncrement(*MI))
return false;
unsigned BasePosLd, OffsetPosLd;
- if (!TII->getBaseAndOffsetPosition(MI, BasePosLd, OffsetPosLd))
+ if (!TII->getBaseAndOffsetPosition(*MI, BasePosLd, OffsetPosLd))
return false;
unsigned BaseReg = MI->getOperand(BasePosLd).getReg();
@@ -3333,11 +3333,11 @@ bool SwingSchedulerDAG::canUseLastOffset
if (!PrevDef || PrevDef == MI)
return false;
- if (!TII->isPostIncrement(PrevDef))
+ if (!TII->isPostIncrement(*PrevDef))
return false;
unsigned BasePos1 = 0, OffsetPos1 = 0;
- if (!TII->getBaseAndOffsetPosition(PrevDef, BasePos1, OffsetPos1))
+ if (!TII->getBaseAndOffsetPosition(*PrevDef, BasePos1, OffsetPos1))
return false;
// Make sure offset values are both positive or both negative.
@@ -3365,7 +3365,7 @@ MachineInstr *SwingSchedulerDAG::applyIn
if (It != InstrChanges.end()) {
std::pair<unsigned, int64_t> RegAndOffset = It->second;
unsigned BasePos, OffsetPos;
- if (!TII->getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
+ if (!TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
return nullptr;
unsigned BaseReg = MI->getOperand(BasePos).getReg();
MachineInstr *LoopDef = findDefInLoop(BaseReg);
@@ -3644,7 +3644,7 @@ bool SMSchedule::orderDependence(SwingSc
continue;
unsigned Reg = MO.getReg();
unsigned BasePos, OffsetPos;
- if (ST.getInstrInfo()->getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
+ if (ST.getInstrInfo()->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
if (MI->getOperand(BasePos).getReg() == Reg)
if (unsigned NewReg = SSD->getInstrBaseReg(SU))
Reg = NewReg;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp?rev=277358&r1=277357&r2=277358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp Mon Aug 1 12:55:48 2016
@@ -670,7 +670,7 @@ void HexagonEarlyIfConversion::predicate
assert(COpc);
MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
MIOperands MO(*MI);
- if (HII->isPostIncrement(MI)) {
+ if (HII->isPostIncrement(*MI)) {
MIB.addOperand(*MO);
++MO;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=277358&r1=277357&r2=277358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Mon Aug 1 12:55:48 2016
@@ -684,18 +684,18 @@ bool HexagonInstrInfo::analyzeLoop(Machi
/// finished. Return the value/register of the new loop count. this function
/// assumes the nth iteration is peeled first.
unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
- MachineInstr *IndVar, MachineInstr *Cmp,
+ MachineInstr *IndVar, MachineInstr &Cmp,
SmallVectorImpl<MachineOperand> &Cond,
SmallVectorImpl<MachineInstr *> &PrevInsts,
unsigned Iter, unsigned MaxIter) const {
// We expect a hardware loop currently. This means that IndVar is set
// to null, and the compare is the ENDLOOP instruction.
- assert((!IndVar) && isEndLoopN(Cmp->getOpcode())
+ assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
&& "Expecting a hardware loop");
MachineFunction *MF = MBB.getParent();
- DebugLoc DL = Cmp->getDebugLoc();
+ DebugLoc DL = Cmp.getDebugLoc();
SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
- MachineInstr *Loop = findLoopInstr(&MBB, Cmp->getOpcode(), VisitedBBs);
+ MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(), VisitedBBs);
if (!Loop)
return 0;
// If the loop trip count is a compile-time value, then just change the
@@ -1346,8 +1346,8 @@ void HexagonInstrInfo::insertNoop(Machin
}
-bool HexagonInstrInfo::isPostIncrement(const MachineInstr *MI) const {
- return getAddrMode(*MI) == HexagonII::PostInc;
+bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
+ return getAddrMode(MI) == HexagonII::PostInc;
}
@@ -1677,14 +1677,14 @@ bool HexagonInstrInfo::areMemAccessesTri
/// If the instruction is an increment of a constant value, return the amount.
-bool HexagonInstrInfo::getIncrementValue(const MachineInstr *MI,
+bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
int &Value) const {
if (isPostIncrement(MI)) {
unsigned AccessSize;
- return getBaseAndOffset(*MI, Value, AccessSize);
+ return getBaseAndOffset(MI, Value, AccessSize);
}
- if (MI->getOpcode() == Hexagon::A2_addi) {
- Value = MI->getOperand(2).getImm();
+ if (MI.getOpcode() == Hexagon::A2_addi) {
+ Value = MI.getOperand(2).getImm();
return true;
}
@@ -3160,7 +3160,7 @@ unsigned HexagonInstrInfo::getBaseAndOff
// Return if it is not a base+offset type instruction or a MemOp.
if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
getAddrMode(MI) != HexagonII::BaseLongOffset &&
- !isMemOp(MI) && !isPostIncrement(&MI))
+ !isMemOp(MI) && !isPostIncrement(MI))
return 0;
// Since it is a memory access instruction, getMemAccessSize() should never
@@ -3175,12 +3175,12 @@ unsigned HexagonInstrInfo::getBaseAndOff
AccessSize = (1U << (getMemAccessSize(MI) - 1));
unsigned basePos = 0, offsetPos = 0;
- if (!getBaseAndOffsetPosition(&MI, basePos, offsetPos))
+ if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
return 0;
// Post increment updates its EA after the mem access,
// so we need to treat its offset as zero.
- if (isPostIncrement(&MI))
+ if (isPostIncrement(MI))
Offset = 0;
else {
Offset = MI.getOperand(offsetPos).getImm();
@@ -3191,22 +3191,22 @@ unsigned HexagonInstrInfo::getBaseAndOff
/// Return the position of the base and offset operands for this instruction.
-bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
+bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
unsigned &BasePos, unsigned &OffsetPos) const {
// Deal with memops first.
- if (isMemOp(*MI)) {
+ if (isMemOp(MI)) {
BasePos = 0;
OffsetPos = 1;
- } else if (MI->mayStore()) {
+ } else if (MI.mayStore()) {
BasePos = 0;
OffsetPos = 1;
- } else if (MI->mayLoad()) {
+ } else if (MI.mayLoad()) {
BasePos = 1;
OffsetPos = 2;
} else
return false;
- if (isPredicated(*MI)) {
+ if (isPredicated(MI)) {
BasePos++;
OffsetPos++;
}
@@ -3215,7 +3215,7 @@ bool HexagonInstrInfo::getBaseAndOffsetP
OffsetPos++;
}
- if (!MI->getOperand(BasePos).isReg() || !MI->getOperand(OffsetPos).isImm())
+ if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
return false;
return true;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=277358&r1=277357&r2=277358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Mon Aug 1 12:55:48 2016
@@ -114,7 +114,7 @@ public:
/// this function when peeling off one or more iterations of a loop. This
/// function assumes the nth iteration is peeled first.
unsigned reduceLoopCount(MachineBasicBlock &MBB,
- MachineInstr *IndVar, MachineInstr *Cmp,
+ MachineInstr *IndVar, MachineInstr &Cmp,
SmallVectorImpl<MachineOperand> &Cond,
SmallVectorImpl<MachineInstr *> &PrevInsts,
unsigned Iter, unsigned MaxIter) const override;
@@ -206,7 +206,7 @@ public:
bool isPredicated(const MachineInstr &MI) const override;
/// Return true for post-incremented instructions.
- bool isPostIncrement(const MachineInstr *MI) const override;
+ bool isPostIncrement(const MachineInstr &MI) const override;
/// Convert the instruction into a predicated instruction.
/// It returns true if the operation was successful.
@@ -274,11 +274,11 @@ public:
/// For instructions with a base and offset, return the position of the
/// base register and offset operands.
- bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
+ bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
unsigned &OffsetPos) const override;
/// If the instruction is an increment of a constant value, return the amount.
- bool getIncrementValue(const MachineInstr *MI, int &Value) const override;
+ bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
/// HexagonInstrInfo specifics.
///
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=277358&r1=277357&r2=277358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Mon Aug 1 12:55:48 2016
@@ -336,17 +336,17 @@ void HexagonSubtarget::adjustSchedDepend
return;
// Don't adjust the latency of post-increment part of the instruction.
- if (QII->isPostIncrement(SrcInst) && Dep.isAssignedRegDep()) {
+ if (QII->isPostIncrement(*SrcInst) && Dep.isAssignedRegDep()) {
if (SrcInst->mayStore())
return;
if (Dep.getReg() != SrcInst->getOperand(0).getReg())
return;
- } else if (QII->isPostIncrement(DstInst) && Dep.getKind() == SDep::Anti) {
+ } else if (QII->isPostIncrement(*DstInst) && Dep.getKind() == SDep::Anti) {
if (DstInst->mayStore())
return;
if (Dep.getReg() != DstInst->getOperand(0).getReg())
return;
- } else if (QII->isPostIncrement(DstInst) && DstInst->mayStore() &&
+ } else if (QII->isPostIncrement(*DstInst) && DstInst->mayStore() &&
Dep.isAssignedRegDep()) {
MachineOperand &Op = DstInst->getOperand(DstInst->getNumOperands() - 1);
if (Op.isReg() && Dep.getReg() != Op.getReg())
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=277358&r1=277357&r2=277358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Mon Aug 1 12:55:48 2016
@@ -497,7 +497,7 @@ static PredicateKind getPredicateSense(c
static const MachineOperand &getPostIncrementOperand(const MachineInstr &MI,
const HexagonInstrInfo *HII) {
- assert(HII->isPostIncrement(&MI) && "Not a post increment operation.");
+ assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
#ifndef NDEBUG
// Post Increment means duplicates. Use dense map to find duplicates in the
// list. Caution: Densemap initializes with the minimum of 64 buckets,
@@ -600,12 +600,12 @@ bool HexagonPacketizerList::canPromoteTo
// Make sure it's NOT the post increment register that we are going to
// new value.
- if (HII->isPostIncrement(&MI) &&
+ if (HII->isPostIncrement(MI) &&
getPostIncrementOperand(MI, HII).getReg() == DepReg) {
return false;
}
- if (HII->isPostIncrement(&PacketMI) && PacketMI.mayLoad() &&
+ if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
// If source is post_inc, or absolute-set addressing, it can not feed
// into new value store
@@ -703,7 +703,7 @@ bool HexagonPacketizerList::canPromoteTo
// The following store can not be dot new.
// Eg. r0 = add(r0, #3)
// memw(r1+r0<<#2) = r0
- if (!HII->isPostIncrement(&MI)) {
+ if (!HII->isPostIncrement(MI)) {
for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
const MachineOperand &MO = MI.getOperand(opNum);
if (MO.isReg() && MO.getReg() == DepReg)
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