[llvm] r277302 - [AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Jul 31 15:19:53 2016
New Revision: 277302

URL: http://llvm.org/viewvc/llvm-project?rev=277302&view=rev
Log:
[AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=277302&r1=277301&r2=277302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun Jul 31 15:19:53 2016
@@ -4845,8 +4845,6 @@ static unsigned getLoadStoreRegOpcode(un
       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
-    if (X86::VR512RegClass.hasSubClassEq(RC))
-      return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
   }
 
   bool HasAVX = STI.hasAVX();
@@ -4924,7 +4922,7 @@ static unsigned getLoadStoreRegOpcode(un
       return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
   case 64:
     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
-    assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
+    assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
     if (isStackAligned)
       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
     else

Modified: llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll?rev=277302&r1=277301&r2=277302&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-intel-ocl.ll Sun Jul 31 15:19:53 2016
@@ -62,11 +62,11 @@ define <16 x float> @testf16_regs(<16 x
 
 ; test calling conventions - prolog and epilog
 ; WIN64-LABEL: test_prolog_epilog
-; WIN64: vmovups %zmm21, {{.*(%rbp).*}}     # 64-byte Spill
-; WIN64: vmovups %zmm6, {{.*(%rbp).*}}     # 64-byte Spill
+; WIN64: vmovaps %zmm21, {{.*(%rbp).*}}     # 64-byte Spill
+; WIN64: vmovaps %zmm6, {{.*(%rbp).*}}     # 64-byte Spill
 ; WIN64: call
-; WIN64: vmovups {{.*(%rbp).*}}, %zmm6      # 64-byte Reload
-; WIN64: vmovups {{.*(%rbp).*}}, %zmm21     # 64-byte Reload
+; WIN64: vmovaps {{.*(%rbp).*}}, %zmm6      # 64-byte Reload
+; WIN64: vmovaps {{.*(%rbp).*}}, %zmm21     # 64-byte Reload
 
 ; X64-LABEL: test_prolog_epilog
 ; X64:  kmovq   %k7, {{.*}}(%rsp)         ## 8-byte Spill