[PATCH] D23000: [X86] Improve 64-bit shifts on 32-bit targets (PR14593)

[Simon Pilgrim via llvm-commits]

RKSimon added inline comments.

================
Comment at: lib/Target/X86/X86ISelLowering.cpp:28675
@@ +28674,3 @@
+            isa<ConstantSDNode>(Op1.getOperand(1)) &&
+            Op1.getConstantOperandVal(1) == 1) {
+          return DAG.getNode(Opc, DL, VT, Op0, Op1.getOperand(0),
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Possibly - I'm interested in being able to match a lot of DAGCombiner patterns for both scalar and vector types.

Currently, at best we only match vector types with 'splatted' constant values - being able to generalize this would be very useful, I've played with some basic all_of style approaches but nothing has been great.

Could your template patterns make this any easier?


Repository:
  rL LLVM

https://reviews.llvm.org/D23000