[PATCH] D23000: [X86] Improve 64-bit shifts on 32-bit targets (PR14593)

[Eli Friedman via llvm-commits]

eli.friedman added a comment.

Might be nice to have a test which triggers this combine without going through legalization.  (Should be possible, I think?)


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Comment at: lib/Target/X86/X86ISelLowering.cpp:28675
@@ +28674,3 @@
+          isa<ConstantSDNode>(Op1.getOperand(1)) &&
+          Op1.getConstantOperandVal(1) == 1) {
+        return DAG.getNode(Opc, DL, VT, Op0, Op1.getOperand(0),
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Maybe it makes sense to split this into two separate if statements; one checking that the two outer shifts match, one checking that the inner shift is a shift by one.  I found it a bit tricky to pick through.  (I sort of wish we had an equivalent to IR pattern matching in SelectionDAG.)


Repository:
  rL LLVM

https://reviews.llvm.org/D23000