[llvm] r277220 - [Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 14:49:42 PDT 2016
Author: kparzysz
Date: Fri Jul 29 16:49:42 2016
New Revision: 277220
URL: http://llvm.org/viewvc/llvm-project?rev=277220&view=rev
Log:
[Hexagon] Referencify MachineInstr in HexagonInstrInfo, NFC
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp
llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp Fri Jul 29 16:49:42 2016
@@ -104,7 +104,7 @@ void HexagonBranchRelaxation::computeOff
}
OffsetMap[&B] = InstOffset;
for (auto &MI : B.instrs())
- InstOffset += HII->getSize(&MI);
+ InstOffset += HII->getSize(MI);
}
}
@@ -152,13 +152,13 @@ bool HexagonBranchRelaxation::isJumpOutO
// Could not analyze it. See if this is something we can recognize.
// If it is a NVJ, it should always have its target in
// a fixed location.
- if (HII->isNewValueJump(&*FirstTerm))
- TBB = FirstTerm->getOperand(HII->getCExtOpNum(&*FirstTerm)).getMBB();
+ if (HII->isNewValueJump(*FirstTerm))
+ TBB = FirstTerm->getOperand(HII->getCExtOpNum(*FirstTerm)).getMBB();
}
if (TBB && &MI == &*FirstTerm) {
Distance = std::abs((long long)InstOffset - BlockToInstOffset[TBB])
+ BranchRelaxSafetyBuffer;
- return !HII->isJumpWithinBranchRange(&*FirstTerm, Distance);
+ return !HII->isJumpWithinBranchRange(*FirstTerm, Distance);
}
if (FBB) {
// Look for second terminator.
@@ -171,7 +171,7 @@ bool HexagonBranchRelaxation::isJumpOutO
// Analyze the second branch in the BB.
Distance = std::abs((long long)InstOffset - BlockToInstOffset[FBB])
+ BranchRelaxSafetyBuffer;
- return !HII->isJumpWithinBranchRange(&*SecondTerm, Distance);
+ return !HII->isJumpWithinBranchRange(*SecondTerm, Distance);
}
return false;
}
@@ -186,16 +186,16 @@ bool HexagonBranchRelaxation::reGenerate
if (!MI.isBranch() || !isJumpOutOfRange(MI, BlockToInstOffset))
continue;
DEBUG(dbgs() << "Long distance jump. isExtendable("
- << HII->isExtendable(&MI) << ") isConstExtended("
- << HII->isConstExtended(&MI) << ") " << MI);
+ << HII->isExtendable(MI) << ") isConstExtended("
+ << HII->isConstExtended(MI) << ") " << MI);
// Since we have not merged HW loops relaxation into
// this code (yet), soften our approach for the moment.
- if (!HII->isExtendable(&MI) && !HII->isExtended(&MI)) {
+ if (!HII->isExtendable(MI) && !HII->isExtended(MI)) {
DEBUG(dbgs() << "\tUnderimplemented relax branch instruction.\n");
} else {
// Find which operand is expandable.
- int ExtOpNum = HII->getCExtOpNum(&MI);
+ int ExtOpNum = HII->getCExtOpNum(MI);
MachineOperand &MO = MI.getOperand(ExtOpNum);
// This need to be something we understand. So far we assume all
// branches have only MBB address as expandable field.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp Fri Jul 29 16:49:42 2016
@@ -385,7 +385,7 @@ HexagonCopyToCombine::findPotentialNewif
continue;
// Mark TFRs that feed a potential new value store as such.
- if (TII->mayBeNewStore(&MI)) {
+ if (TII->mayBeNewStore(MI)) {
// Look for uses of TFR instructions.
for (unsigned OpdIdx = 0, OpdE = MI.getNumOperands(); OpdIdx != OpdE;
++OpdIdx) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp Fri Jul 29 16:49:42 2016
@@ -125,7 +125,7 @@ bool HexagonFixupHwLoops::fixupLoopInstr
BlockToInstOffset[&MBB] = InstOffset;
for (const MachineInstr &MI : MBB)
- InstOffset += HII->getSize(&MI);
+ InstOffset += HII->getSize(MI);
}
// Second pass - check each loop instruction to see if it needs to be
@@ -138,7 +138,7 @@ bool HexagonFixupHwLoops::fixupLoopInstr
MachineBasicBlock::iterator MII = MBB.begin();
MachineBasicBlock::iterator MIE = MBB.end();
while (MII != MIE) {
- InstOffset += HII->getSize(&*MII);
+ InstOffset += HII->getSize(*MII);
if (MII->isDebugValue()) {
++MII;
continue;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Fri Jul 29 16:49:42 2016
@@ -2001,7 +2001,7 @@ void HexagonFrameLowering::optimizeSpill
// this restriction.
if (Load || Store) {
int TFI = Load ? LFI : SFI;
- unsigned AM = HII.getAddrMode(&In);
+ unsigned AM = HII.getAddrMode(In);
SlotInfo &SI = FIRangeMap[TFI];
bool Bad = (AM != HexagonII::BaseImmOffset);
if (!Bad) {
@@ -2016,7 +2016,7 @@ void HexagonFrameLowering::optimizeSpill
}
if (!Bad) {
// Check sizes.
- unsigned S = (1U << (HII.getMemAccessSize(&In) - 1));
+ unsigned S = (1U << (HII.getMemAccessSize(In) - 1));
if (SI.Size != 0 && SI.Size != S)
Bad = true;
else
@@ -2166,15 +2166,15 @@ void HexagonFrameLowering::optimizeSpill
if (!IndexType::isInstr(Range.start()) ||
!IndexType::isInstr(Range.end()))
continue;
- MachineInstr *SI = IM.getInstr(Range.start());
- MachineInstr *EI = IM.getInstr(Range.end());
- assert(SI->mayStore() && "Unexpected start instruction");
- assert(EI->mayLoad() && "Unexpected end instruction");
- MachineOperand &SrcOp = SI->getOperand(2);
+ MachineInstr &SI = *IM.getInstr(Range.start());
+ MachineInstr &EI = *IM.getInstr(Range.end());
+ assert(SI.mayStore() && "Unexpected start instruction");
+ assert(EI.mayLoad() && "Unexpected end instruction");
+ MachineOperand &SrcOp = SI.getOperand(2);
HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
SrcOp.getSubReg() };
- auto *RC = HII.getRegClass(SI->getDesc(), 2, &HRI, MF);
+ auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
// The this-> is needed to unconfuse MSVC.
unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n');
@@ -2189,10 +2189,10 @@ void HexagonFrameLowering::optimizeSpill
#endif
// Generate the copy-in: "FoundR = COPY SrcR" at the store location.
- MachineBasicBlock::iterator StartIt = SI, NextIt;
+ MachineBasicBlock::iterator StartIt = SI.getIterator(), NextIt;
MachineInstr *CopyIn = nullptr;
if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) {
- const DebugLoc &DL = SI->getDebugLoc();
+ const DebugLoc &DL = SI.getDebugLoc();
CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
.addOperand(SrcOp);
}
@@ -2209,33 +2209,33 @@ void HexagonFrameLowering::optimizeSpill
// We are keeping this register live.
SrcOp.setIsKill(false);
} else {
- B.erase(SI);
- IM.replaceInstr(SI, CopyIn);
+ B.erase(&SI);
+ IM.replaceInstr(&SI, CopyIn);
}
- auto EndIt = std::next(MachineBasicBlock::iterator(EI));
+ auto EndIt = std::next(EI.getIterator());
for (auto It = StartIt; It != EndIt; It = NextIt) {
- MachineInstr *MI = &*It;
+ MachineInstr &MI = *It;
NextIt = std::next(It);
int TFI;
- if (!HII.isLoadFromStackSlot(*MI, TFI) || TFI != FI)
+ if (!HII.isLoadFromStackSlot(MI, TFI) || TFI != FI)
continue;
- unsigned DstR = MI->getOperand(0).getReg();
- assert(MI->getOperand(0).getSubReg() == 0);
+ unsigned DstR = MI.getOperand(0).getReg();
+ assert(MI.getOperand(0).getSubReg() == 0);
MachineInstr *CopyOut = nullptr;
if (DstR != FoundR) {
- DebugLoc DL = MI->getDebugLoc();
+ DebugLoc DL = MI.getDebugLoc();
unsigned MemSize = (1U << (HII.getMemAccessSize(MI) - 1));
assert(HII.getAddrMode(MI) == HexagonII::BaseImmOffset);
unsigned CopyOpc = TargetOpcode::COPY;
- if (HII.isSignExtendingLoad(*MI))
+ if (HII.isSignExtendingLoad(MI))
CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
- else if (HII.isZeroExtendingLoad(*MI))
+ else if (HII.isZeroExtendingLoad(MI))
CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
- .addReg(FoundR, getKillRegState(MI == EI));
+ .addReg(FoundR, getKillRegState(&MI == &EI));
}
- IM.replaceInstr(MI, CopyOut);
+ IM.replaceInstr(&MI, CopyOut);
B.erase(It);
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp Fri Jul 29 16:49:42 2016
@@ -1038,7 +1038,7 @@ void HexagonGenInsert::pruneCoveredSets(
// If there exists a candidate with a non-empty set, the ones with empty
// sets will not be used and can be removed.
MachineInstr *DefVR = MRI->getVRegDef(VR);
- bool DefEx = HII->isConstExtended(DefVR);
+ bool DefEx = HII->isConstExtended(*DefVR);
bool HasNE = false;
for (unsigned i = 0, n = LL.size(); i < n; ++i) {
if (LL[i].second.empty())
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHazardRecognizer.cpp Fri Jul 29 16:49:42 2016
@@ -42,7 +42,7 @@ HexagonHazardRecognizer::getHazardType(S
if (!Resources->canReserveResources(*MI)) {
DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
HazardType RetVal = Hazard;
- if (TII->mayBeNewStore(MI)) {
+ if (TII->mayBeNewStore(*MI)) {
// Make sure the register to be stored is defined by an instruction in the
// packet.
MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
@@ -52,7 +52,7 @@ HexagonHazardRecognizer::getHazardType(S
// causes a hazard.
MachineFunction *MF = MI->getParent()->getParent();
MachineInstr *NewMI =
- MF->CreateMachineInstr(TII->get(TII->getDotNewOp(MI)),
+ MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
MI->getDebugLoc());
if (Resources->canReserveResources(*NewMI))
RetVal = NoHazard;
@@ -106,10 +106,11 @@ void HexagonHazardRecognizer::EmitInstru
if (!Resources->canReserveResources(*MI)) {
// It must be a .new store since other instructions must be able to be
// reserved at this point.
- assert(TII->mayBeNewStore(MI) && "Expecting .new store");
+ assert(TII->mayBeNewStore(*MI) && "Expecting .new store");
MachineFunction *MF = MI->getParent()->getParent();
- MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(TII->getDotNewOp(MI)),
- MI->getDebugLoc());
+ MachineInstr *NewMI =
+ MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
+ MI->getDebugLoc());
assert(Resources->canReserveResources(*NewMI));
Resources->reserveResources(*NewMI);
MF->DeleteMachineInstr(NewMI);
@@ -123,7 +124,7 @@ void HexagonHazardRecognizer::EmitInstru
// schedule it before other instructions. We only do this if the use has
// the same height as the dot cur. Otherwise, we may miss scheduling an
// instruction with a greater height, which is more important.
- if (TII->mayBeCurLoad(MI))
+ if (TII->mayBeCurLoad(*MI))
for (auto &S : SU->Succs)
if (S.isAssignedRegDep() && S.getLatency() == 0 &&
SU->getHeight() == S.getSUnit()->getHeight()) {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri Jul 29 16:49:42 2016
@@ -177,13 +177,13 @@ static MachineInstr *findLoopInstr(Machi
/// Gather register def/uses from MI.
/// This treats possible (predicated) defs as actually happening ones
/// (conservatively).
-static inline void parseOperands(const MachineInstr *MI,
+static inline void parseOperands(const MachineInstr &MI,
SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
Defs.clear();
Uses.clear();
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg())
continue;
@@ -458,7 +458,7 @@ bool HexagonInstrInfo::analyzeBranch(Mac
return true;
bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
- bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
+ bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
return true;
@@ -496,7 +496,7 @@ bool HexagonInstrInfo::analyzeBranch(Mac
}
bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
- bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
+ bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
if (!SecondLastInst->getOperand(1).isMBB())
return true;
@@ -1346,6 +1346,11 @@ void HexagonInstrInfo::insertNoop(Machin
}
+bool HexagonInstrInfo::isPostIncrement(const MachineInstr *MI) const {
+ return getAddrMode(*MI) == HexagonII::PostInc;
+}
+
+
// Returns true if an instruction is predicated irrespective of the predicate
// sense. For example, all of the following will return true.
// if (p0) R1 = add(R2, R3)
@@ -1615,7 +1620,7 @@ bool HexagonInstrInfo::analyzeCompare(co
unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr &MI,
unsigned *PredCost) const {
- return getInstrTimingClassLatency(ItinData, &MI);
+ return getInstrTimingClassLatency(ItinData, MI);
}
@@ -1641,16 +1646,16 @@ bool HexagonInstrInfo::areMemAccessesTri
// Instructions that are pure loads, not loads and stores like memops are not
// dependent.
- if (MIa.mayLoad() && !isMemOp(&MIa) && MIb.mayLoad() && !isMemOp(&MIb))
+ if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
return true;
// Get base, offset, and access size in MIa.
- unsigned BaseRegA = getBaseAndOffset(&MIa, OffsetA, SizeA);
+ unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
if (!BaseRegA || !SizeA)
return false;
// Get base, offset, and access size in MIb.
- unsigned BaseRegB = getBaseAndOffset(&MIb, OffsetB, SizeB);
+ unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
if (!BaseRegB || !SizeB)
return false;
@@ -1676,7 +1681,7 @@ bool HexagonInstrInfo::getIncrementValue
int &Value) const {
if (isPostIncrement(MI)) {
unsigned AccessSize;
- return getBaseAndOffset(MI, Value, AccessSize);
+ return getBaseAndOffset(*MI, Value, AccessSize);
}
if (MI->getOpcode() == Hexagon::A2_addi) {
Value = MI->getOperand(2).getImm();
@@ -1687,7 +1692,7 @@ bool HexagonInstrInfo::getIncrementValue
}
-unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
+unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetRegisterClass *TRC;
if (VT == MVT::i1) {
@@ -1705,32 +1710,32 @@ unsigned HexagonInstrInfo::createVR(Mach
}
-bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr* MI) const {
+bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
return (getAddrMode(MI) == HexagonII::AbsoluteSet);
}
-bool HexagonInstrInfo::isAccumulator(const MachineInstr *MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
}
-bool HexagonInstrInfo::isComplex(const MachineInstr *MI) const {
- const MachineFunction *MF = MI->getParent()->getParent();
+bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
+ const MachineFunction *MF = MI.getParent()->getParent();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
if (!(isTC1(MI))
&& !(QII->isTC2Early(MI))
- && !(MI->getDesc().mayLoad())
- && !(MI->getDesc().mayStore())
- && (MI->getDesc().getOpcode() != Hexagon::S2_allocframe)
- && (MI->getDesc().getOpcode() != Hexagon::L2_deallocframe)
+ && !(MI.getDesc().mayLoad())
+ && !(MI.getDesc().mayStore())
+ && (MI.getDesc().getOpcode() != Hexagon::S2_allocframe)
+ && (MI.getDesc().getOpcode() != Hexagon::L2_deallocframe)
&& !(QII->isMemOp(MI))
- && !(MI->isBranch())
- && !(MI->isReturn())
- && !MI->isCall())
+ && !(MI.isBranch())
+ && !(MI.isReturn())
+ && !MI.isCall())
return true;
return false;
@@ -1738,24 +1743,24 @@ bool HexagonInstrInfo::isComplex(const M
// Return true if the instruction is a compund branch instruction.
-bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr *MI) const {
- return (getType(MI) == HexagonII::TypeCOMPOUND && MI->isBranch());
+bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
+ return (getType(MI) == HexagonII::TypeCOMPOUND && MI.isBranch());
}
-bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const {
- return (MI->isBranch() && isPredicated(*MI)) ||
+bool HexagonInstrInfo::isCondInst(const MachineInstr &MI) const {
+ return (MI.isBranch() && isPredicated(MI)) ||
isConditionalTransfer(MI) ||
isConditionalALU32(MI) ||
isConditionalLoad(MI) ||
// Predicated stores which don't have a .new on any operands.
- (MI->mayStore() && isPredicated(*MI) && !isNewValueStore(MI) &&
- !isPredicatedNew(*MI));
+ (MI.mayStore() && isPredicated(MI) && !isNewValueStore(MI) &&
+ !isPredicatedNew(MI));
}
-bool HexagonInstrInfo::isConditionalALU32(const MachineInstr* MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isConditionalALU32(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::A2_paddf:
case Hexagon::A2_paddfnew:
case Hexagon::A2_paddif:
@@ -1814,11 +1819,11 @@ bool HexagonInstrInfo::isConditionalALU3
// FIXME - Function name and it's functionality don't match.
// It should be renamed to hasPredNewOpcode()
-bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const {
- if (!MI->getDesc().mayLoad() || !isPredicated(*MI))
+bool HexagonInstrInfo::isConditionalLoad(const MachineInstr &MI) const {
+ if (!MI.getDesc().mayLoad() || !isPredicated(MI))
return false;
- int PNewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
+ int PNewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
// Instruction with valid predicated-new opcode can be promoted to .new.
return PNewOpcode >= 0;
}
@@ -1828,8 +1833,8 @@ bool HexagonInstrInfo::isConditionalLoad
//
// Note: It doesn't include conditional new-value stores as they can't be
// converted to .new predicate.
-bool HexagonInstrInfo::isConditionalStore(const MachineInstr* MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isConditionalStore(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
default: return false;
case Hexagon::S4_storeirbt_io:
case Hexagon::S4_storeirbf_io:
@@ -1882,8 +1887,8 @@ bool HexagonInstrInfo::isConditionalStor
}
-bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::A2_tfrt:
case Hexagon::A2_tfrf:
case Hexagon::C2_cmoveit:
@@ -1905,8 +1910,8 @@ bool HexagonInstrInfo::isConditionalTran
// TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
// isFPImm and later getFPImm as well.
-bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
if (isExtended) // Instruction must be extended.
return true;
@@ -1916,11 +1921,11 @@ bool HexagonInstrInfo::isConstExtended(c
if (!isExtendable)
return false;
- if (MI->isCall())
+ if (MI.isCall())
return false;
short ExtOpNum = getCExtOpNum(MI);
- const MachineOperand &MO = MI->getOperand(ExtOpNum);
+ const MachineOperand &MO = MI.getOperand(ExtOpNum);
// Use MO operand flags to determine if MO
// has the HMOTF_ConstExtended flag set.
if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
@@ -1952,8 +1957,8 @@ bool HexagonInstrInfo::isConstExtended(c
}
-bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::L4_return :
case Hexagon::L4_return_t :
case Hexagon::L4_return_f :
@@ -1968,10 +1973,9 @@ bool HexagonInstrInfo::isDeallocRet(cons
// Return true when ConsMI uses a register defined by ProdMI.
-bool HexagonInstrInfo::isDependent(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) const {
- const MCInstrDesc &ProdMCID = ProdMI->getDesc();
- if (!ProdMCID.getNumDefs())
+bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) const {
+ if (!ProdMI.getDesc().getNumDefs())
return false;
auto &HRI = getRegisterInfo();
@@ -2006,8 +2010,8 @@ bool HexagonInstrInfo::isDependent(const
// Returns true if the instruction is alread a .cur.
-bool HexagonInstrInfo::isDotCurInst(const MachineInstr* MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::V6_vL32b_cur_pi:
case Hexagon::V6_vL32b_cur_ai:
case Hexagon::V6_vL32b_cur_pi_128B:
@@ -2020,8 +2024,8 @@ bool HexagonInstrInfo::isDotCurInst(cons
// Returns true, if any one of the operands is a dot new
// insn, whether it is predicated dot new or register dot new.
-bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const {
- if (isNewValueInst(MI) || (isPredicated(*MI) && isPredicatedNew(*MI)))
+bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
+ if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
return true;
return false;
@@ -2029,23 +2033,20 @@ bool HexagonInstrInfo::isDotNewInst(cons
/// Symmetrical. See if these two instructions are fit for duplex pair.
-bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa,
- const MachineInstr *MIb) const {
+bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
+ const MachineInstr &MIb) const {
HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
}
-bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr *MI) const {
- if (!MI)
- return false;
-
- if (MI->mayLoad() || MI->mayStore() || MI->isCompare())
+bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr &MI) const {
+ if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
return true;
// Multiply
- unsigned SchedClass = MI->getDesc().getSchedClass();
+ unsigned SchedClass = MI.getDesc().getSchedClass();
if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
return true;
return false;
@@ -2073,15 +2074,15 @@ bool HexagonInstrInfo::isExpr(unsigned O
}
-bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
- const MCInstrDesc &MID = MI->getDesc();
+bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
+ const MCInstrDesc &MID = MI.getDesc();
const uint64_t F = MID.TSFlags;
if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
return true;
// TODO: This is largely obsolete now. Will need to be removed
// in consecutive patches.
- switch(MI->getOpcode()) {
+ switch (MI.getOpcode()) {
// TFR_FI Remains a special case.
case Hexagon::TFR_FI:
return true;
@@ -2095,15 +2096,15 @@ bool HexagonInstrInfo::isExtendable(cons
// This returns true in two cases:
// - The OP code itself indicates that this is an extended instruction.
// - One of MOs has been marked with HMOTF_ConstExtended flag.
-bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
+bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
// First check if this is permanently extended op code.
- const uint64_t F = MI->getDesc().TSFlags;
+ const uint64_t F = MI.getDesc().TSFlags;
if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
return true;
// Use MO operand flags to determine if one of MI's operands
// has HMOTF_ConstExtended flag set.
- for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
- E = MI->operands_end(); I != E; ++I) {
+ for (MachineInstr::const_mop_iterator I = MI.operands_begin(),
+ E = MI.operands_end(); I != E; ++I) {
if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
return true;
}
@@ -2111,26 +2112,26 @@ bool HexagonInstrInfo::isExtended(const
}
-bool HexagonInstrInfo::isFloat(const MachineInstr *MI) const {
- unsigned Opcode = MI->getOpcode();
+bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
+ unsigned Opcode = MI.getOpcode();
const uint64_t F = get(Opcode).TSFlags;
return (F >> HexagonII::FPPos) & HexagonII::FPMask;
}
// No V60 HVX VMEM with A_INDIRECT.
-bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr *I,
- const MachineInstr *J) const {
+bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
+ const MachineInstr &J) const {
if (!isV60VectorInstruction(I))
return false;
- if (!I->mayLoad() && !I->mayStore())
+ if (!I.mayLoad() && !I.mayStore())
return false;
- return J->isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
+ return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
}
-bool HexagonInstrInfo::isIndirectCall(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::J2_callr :
case Hexagon::J2_callrf :
case Hexagon::J2_callrt :
@@ -2140,8 +2141,8 @@ bool HexagonInstrInfo::isIndirectCall(co
}
-bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::L4_return :
case Hexagon::L4_return_t :
case Hexagon::L4_return_f :
@@ -2155,8 +2156,8 @@ bool HexagonInstrInfo::isIndirectL4Retur
}
-bool HexagonInstrInfo::isJumpR(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::J2_jumpr :
case Hexagon::J2_jumprt :
case Hexagon::J2_jumprf :
@@ -2174,14 +2175,14 @@ bool HexagonInstrInfo::isJumpR(const Mac
// Use abs estimate as oppose to the exact number.
// TODO: This will need to be changed to use MC level
// definition of instruction extendable field size.
-bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr *MI,
+bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
unsigned offset) const {
// This selection of jump instructions matches to that what
// AnalyzeBranch can parse, plus NVJ.
if (isNewValueJump(MI)) // r9:2
return isInt<11>(offset);
- switch (MI->getOpcode()) {
+ switch (MI.getOpcode()) {
// Still missing Jump to address condition on register value.
default:
return false;
@@ -2215,18 +2216,15 @@ bool HexagonInstrInfo::isJumpWithinBranc
}
-bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
- const MachineInstr *ESMI) const {
- if (!LRMI || !ESMI)
- return false;
-
+bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
+ const MachineInstr &ESMI) const {
bool isLate = isLateResultInstr(LRMI);
bool isEarly = isEarlySourceInstr(ESMI);
DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
- DEBUG(LRMI->dump());
+ DEBUG(LRMI.dump());
DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
- DEBUG(ESMI->dump());
+ DEBUG(ESMI.dump());
if (isLate && isEarly) {
DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
@@ -2237,11 +2235,8 @@ bool HexagonInstrInfo::isLateInstrFeedsE
}
-bool HexagonInstrInfo::isLateResultInstr(const MachineInstr *MI) const {
- if (!MI)
- return false;
-
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isLateResultInstr(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case TargetOpcode::EXTRACT_SUBREG:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:
@@ -2255,7 +2250,7 @@ bool HexagonInstrInfo::isLateResultInstr
break;
}
- unsigned SchedClass = MI->getDesc().getSchedClass();
+ unsigned SchedClass = MI.getDesc().getSchedClass();
switch (SchedClass) {
case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
@@ -2277,18 +2272,15 @@ bool HexagonInstrInfo::isLateResultInstr
}
-bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr *MI) const {
- if (!MI)
- return false;
-
+bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
// Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
// resource, but all operands can be received late like an ALU instruction.
- return MI->getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
+ return MI.getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
}
-bool HexagonInstrInfo::isLoopN(const MachineInstr *MI) const {
- unsigned Opcode = MI->getOpcode();
+bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
+ unsigned Opcode = MI.getOpcode();
return Opcode == Hexagon::J2_loop0i ||
Opcode == Hexagon::J2_loop0r ||
Opcode == Hexagon::J2_loop0iext ||
@@ -2300,8 +2292,8 @@ bool HexagonInstrInfo::isLoopN(const Mac
}
-bool HexagonInstrInfo::isMemOp(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
default: return false;
case Hexagon::L4_iadd_memopw_io :
case Hexagon::L4_isub_memopw_io :
@@ -2333,8 +2325,8 @@ bool HexagonInstrInfo::isMemOp(const Mac
}
-bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
}
@@ -2345,13 +2337,13 @@ bool HexagonInstrInfo::isNewValue(unsign
}
-bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
+bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
return isNewValueJump(MI) || isNewValueStore(MI);
}
-bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
- return isNewValue(MI) && MI->isBranch();
+bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
+ return isNewValue(MI) && MI.isBranch();
}
@@ -2360,8 +2352,8 @@ bool HexagonInstrInfo::isNewValueJump(un
}
-bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
}
@@ -2373,19 +2365,14 @@ bool HexagonInstrInfo::isNewValueStore(u
// Returns true if a particular operand is extendable for an instruction.
-bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
+bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
unsigned OperandNum) const {
- const uint64_t F = MI->getDesc().TSFlags;
+ const uint64_t F = MI.getDesc().TSFlags;
return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
== OperandNum;
}
-bool HexagonInstrInfo::isPostIncrement(const MachineInstr* MI) const {
- return getAddrMode(MI) == HexagonII::PostInc;
-}
-
-
bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
const uint64_t F = MI.getDesc().TSFlags;
assert(isPredicated(MI));
@@ -2436,11 +2423,11 @@ bool HexagonInstrInfo::isPredictedTaken(
}
-bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
- return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
- MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
- MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
- MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
+bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
+ return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
+ MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
+ MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
+ MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
}
bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
@@ -2522,14 +2509,14 @@ bool HexagonInstrInfo::isSignExtendingLo
}
-bool HexagonInstrInfo::isSolo(const MachineInstr* MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
}
-bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const {
- switch (MI->getOpcode()) {
+bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
case Hexagon::STriw_pred :
case Hexagon::LDriw_pred :
return true;
@@ -2539,11 +2526,11 @@ bool HexagonInstrInfo::isSpillPredRegOp(
}
-bool HexagonInstrInfo::isTailCall(const MachineInstr *MI) const {
- if (!MI->isBranch())
+bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
+ if (!MI.isBranch())
return false;
- for (auto &Op : MI->operands())
+ for (auto &Op : MI.operands())
if (Op.isGlobal() || Op.isSymbol())
return true;
return false;
@@ -2551,8 +2538,8 @@ bool HexagonInstrInfo::isTailCall(const
// Returns true when SU has a timing class TC1.
-bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const {
- unsigned SchedClass = MI->getDesc().getSchedClass();
+bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
+ unsigned SchedClass = MI.getDesc().getSchedClass();
switch (SchedClass) {
case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
@@ -2570,8 +2557,8 @@ bool HexagonInstrInfo::isTC1(const Machi
}
-bool HexagonInstrInfo::isTC2(const MachineInstr *MI) const {
- unsigned SchedClass = MI->getDesc().getSchedClass();
+bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
+ unsigned SchedClass = MI.getDesc().getSchedClass();
switch (SchedClass) {
case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
case Hexagon::Sched::ALU64_tc_2_SLOT23:
@@ -2587,8 +2574,8 @@ bool HexagonInstrInfo::isTC2(const Machi
}
-bool HexagonInstrInfo::isTC2Early(const MachineInstr *MI) const {
- unsigned SchedClass = MI->getDesc().getSchedClass();
+bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
+ unsigned SchedClass = MI.getDesc().getSchedClass();
switch (SchedClass) {
case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
@@ -2608,41 +2595,33 @@ bool HexagonInstrInfo::isTC2Early(const
}
-bool HexagonInstrInfo::isTC4x(const MachineInstr *MI) const {
- if (!MI)
- return false;
-
- unsigned SchedClass = MI->getDesc().getSchedClass();
+bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
+ unsigned SchedClass = MI.getDesc().getSchedClass();
return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
}
// Schedule this ASAP.
-bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr *MI1,
- const MachineInstr *MI2) const {
- if (!MI1 || !MI2)
- return false;
+bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
+ const MachineInstr &MI2) const {
if (mayBeCurLoad(MI1)) {
// if (result of SU is used in Next) return true;
- unsigned DstReg = MI1->getOperand(0).getReg();
- int N = MI2->getNumOperands();
+ unsigned DstReg = MI1.getOperand(0).getReg();
+ int N = MI2.getNumOperands();
for (int I = 0; I < N; I++)
- if (MI2->getOperand(I).isReg() && DstReg == MI2->getOperand(I).getReg())
+ if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
return true;
}
if (mayBeNewStore(MI2))
- if (MI2->getOpcode() == Hexagon::V6_vS32b_pi)
- if (MI1->getOperand(0).isReg() && MI2->getOperand(3).isReg() &&
- MI1->getOperand(0).getReg() == MI2->getOperand(3).getReg())
+ if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
+ if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
+ MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
return true;
return false;
}
-bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr *MI) const {
- if (!MI)
- return false;
-
+bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr &MI) const {
const uint64_t V = getType(MI);
return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
}
@@ -2854,15 +2833,13 @@ bool HexagonInstrInfo::isValidOffset(uns
}
-bool HexagonInstrInfo::isVecAcc(const MachineInstr *MI) const {
- return MI && isV60VectorInstruction(MI) && isAccumulator(MI);
+bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
+ return isV60VectorInstruction(MI) && isAccumulator(MI);
}
-bool HexagonInstrInfo::isVecALU(const MachineInstr *MI) const {
- if (!MI)
- return false;
- const uint64_t F = get(MI->getOpcode()).TSFlags;
+bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
+ const uint64_t F = get(MI.getOpcode()).TSFlags;
const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
return
V == HexagonII::TypeCVI_VA ||
@@ -2870,8 +2847,8 @@ bool HexagonInstrInfo::isVecALU(const Ma
}
-bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) const {
+bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) const {
if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
return true;
@@ -2964,8 +2941,8 @@ bool HexagonInstrInfo::isZeroExtendingLo
// Add latency to instruction.
-bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr *MI1,
- const MachineInstr *MI2) const {
+bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
+ const MachineInstr &MI2) const {
if (isV60VectorInstruction(MI1) && isV60VectorInstruction(MI2))
if (!isVecUsableNextPacket(MI1, MI2))
return true;
@@ -2979,26 +2956,26 @@ bool HexagonInstrInfo::getMemOpBaseRegIm
const {
unsigned AccessSize = 0;
int OffsetVal = 0;
- BaseReg = getBaseAndOffset(&LdSt, OffsetVal, AccessSize);
+ BaseReg = getBaseAndOffset(LdSt, OffsetVal, AccessSize);
Offset = OffsetVal;
return BaseReg != 0;
}
/// \brief Can these instructions execute at the same time in a bundle.
-bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr *First,
- const MachineInstr *Second) const {
+bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
+ const MachineInstr &Second) const {
if (DisableNVSchedule)
return false;
if (mayBeNewStore(Second)) {
// Make sure the definition of the first instruction is the value being
// stored.
const MachineOperand &Stored =
- Second->getOperand(Second->getNumOperands() - 1);
+ Second.getOperand(Second.getNumOperands() - 1);
if (!Stored.isReg())
return false;
- for (unsigned i = 0, e = First->getNumOperands(); i < e; ++i) {
- const MachineOperand &Op = First->getOperand(i);
+ for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
+ const MachineOperand &Op = First.getOperand(i);
if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
return true;
}
@@ -3017,30 +2994,30 @@ bool HexagonInstrInfo::hasEHLabel(const
// Returns true if an instruction can be converted into a non-extended
// equivalent instruction.
-bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr *MI) const {
+bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
short NonExtOpcode;
// Check if the instruction has a register form that uses register in place
// of the extended operand, if so return that as the non-extended form.
- if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
+ if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
return true;
- if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
+ if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
// Check addressing mode and retrieve non-ext equivalent instruction.
switch (getAddrMode(MI)) {
case HexagonII::Absolute :
// Load/store with absolute addressing mode can be converted into
// base+offset mode.
- NonExtOpcode = Hexagon::getBaseWithImmOffset(MI->getOpcode());
+ NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.getOpcode());
break;
case HexagonII::BaseImmOffset :
// Load/store with base+offset addressing mode can be converted into
// base+register offset addressing mode. However left shift operand should
// be set to 0.
- NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
+ NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.getOpcode());
break;
case HexagonII::BaseLongOffset:
- NonExtOpcode = Hexagon::getRegShlForm(MI->getOpcode());
+ NonExtOpcode = Hexagon::getRegShlForm(MI.getOpcode());
break;
default:
return false;
@@ -3053,8 +3030,8 @@ bool HexagonInstrInfo::hasNonExtEquivale
}
-bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr *MI) const {
- return Hexagon::getRealHWInstr(MI->getOpcode(),
+bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
+ return Hexagon::getRealHWInstr(MI.getOpcode(),
Hexagon::InstrType_Pseudo) >= 0;
}
@@ -3072,23 +3049,23 @@ bool HexagonInstrInfo::hasUncondBranch(c
// Returns true, if a LD insn can be promoted to a cur load.
-bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr *MI) const {
- auto &HST = MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>();
- const uint64_t F = MI->getDesc().TSFlags;
+bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
+ auto &HST = MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>();
+ const uint64_t F = MI.getDesc().TSFlags;
return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
HST.hasV60TOps();
}
// Returns true, if a ST insn can be promoted to a new-value store.
-bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
}
-bool HexagonInstrInfo::producesStall(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) const {
+bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) const {
// There is no stall when ProdMI is not a V60 vector.
if (!isV60VectorInstruction(ProdMI))
return false;
@@ -3106,7 +3083,7 @@ bool HexagonInstrInfo::producesStall(con
}
-bool HexagonInstrInfo::producesStall(const MachineInstr *MI,
+bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
MachineBasicBlock::const_instr_iterator BII) const {
// There is no stall when I is not a V60 vector.
if (!isV60VectorInstruction(MI))
@@ -3115,8 +3092,8 @@ bool HexagonInstrInfo::producesStall(con
MachineBasicBlock::const_instr_iterator MII = BII;
MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
- if (!(*MII).isBundle()) {
- const MachineInstr *J = &*MII;
+ if (!MII->isBundle()) {
+ const MachineInstr &J = *MII;
if (!isV60VectorInstruction(J))
return false;
else if (isVecUsableNextPacket(J, MI))
@@ -3125,7 +3102,7 @@ bool HexagonInstrInfo::producesStall(con
}
for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
- const MachineInstr *J = &*MII;
+ const MachineInstr &J = *MII;
if (producesStall(J, MI))
return true;
}
@@ -3133,10 +3110,10 @@ bool HexagonInstrInfo::producesStall(con
}
-bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr *MI,
+bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
unsigned PredReg) const {
- for (unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
- const MachineOperand &MO = MI->getOperand(opNum);
+ for (unsigned opNum = 0; opNum < MI.getNumOperands(); opNum++) {
+ const MachineOperand &MO = MI.getOperand(opNum);
if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
return false; // Predicate register must be explicitly defined.
}
@@ -3144,7 +3121,7 @@ bool HexagonInstrInfo::predCanBeUsedAsDo
// Hexagon Programmer's Reference says that decbin, memw_locked, and
// memd_locked cannot be used as .new as well,
// but we don't seem to have these instructions defined.
- return MI->getOpcode() != Hexagon::A4_tlbmatch;
+ return MI.getOpcode() != Hexagon::A4_tlbmatch;
}
@@ -3165,25 +3142,25 @@ bool HexagonInstrInfo::predOpcodeHasNot(
}
-short HexagonInstrInfo::getAbsoluteForm(const MachineInstr *MI) const {
- return Hexagon::getAbsoluteForm(MI->getOpcode());
+short HexagonInstrInfo::getAbsoluteForm(const MachineInstr &MI) const {
+ return Hexagon::getAbsoluteForm(MI.getOpcode());
}
-unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
}
// Returns the base register in a memory access (load/store). The offset is
// returned in Offset and the access size is returned in AccessSize.
-unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr *MI,
+unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
int &Offset, unsigned &AccessSize) const {
// Return if it is not a base+offset type instruction or a MemOp.
if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
getAddrMode(MI) != HexagonII::BaseLongOffset &&
- !isMemOp(MI) && !isPostIncrement(MI))
+ !isMemOp(MI) && !isPostIncrement(&MI))
return 0;
// Since it is a memory access instruction, getMemAccessSize() should never
@@ -3198,18 +3175,18 @@ unsigned HexagonInstrInfo::getBaseAndOff
AccessSize = (1U << (getMemAccessSize(MI) - 1));
unsigned basePos = 0, offsetPos = 0;
- if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
+ if (!getBaseAndOffsetPosition(&MI, basePos, offsetPos))
return 0;
// Post increment updates its EA after the mem access,
// so we need to treat its offset as zero.
- if (isPostIncrement(MI))
+ if (isPostIncrement(&MI))
Offset = 0;
else {
- Offset = MI->getOperand(offsetPos).getImm();
+ Offset = MI.getOperand(offsetPos).getImm();
}
- return MI->getOperand(basePos).getReg();
+ return MI.getOperand(basePos).getReg();
}
@@ -3217,7 +3194,7 @@ unsigned HexagonInstrInfo::getBaseAndOff
bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
unsigned &BasePos, unsigned &OffsetPos) const {
// Deal with memops first.
- if (isMemOp(MI)) {
+ if (isMemOp(*MI)) {
BasePos = 0;
OffsetPos = 1;
} else if (MI->mayStore()) {
@@ -3314,29 +3291,29 @@ short HexagonInstrInfo::getBaseWithLongO
}
-short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr *MI) const {
- return Hexagon::getBaseWithLongOffset(MI->getOpcode());
+short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr &MI) const {
+ return Hexagon::getBaseWithLongOffset(MI.getOpcode());
}
-short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr *MI) const {
- return Hexagon::getBaseWithRegOffset(MI->getOpcode());
+short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr &MI) const {
+ return Hexagon::getBaseWithRegOffset(MI.getOpcode());
}
// Returns Operand Index for the constant extended instruction.
-unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
}
// See if instruction could potentially be a duplex candidate.
// If so, return its group. Zero otherwise.
HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
- const MachineInstr *MI) const {
+ const MachineInstr &MI) const {
unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
- switch (MI->getOpcode()) {
+ switch (MI.getOpcode()) {
default:
return HexagonII::HCG_None;
//
@@ -3348,9 +3325,9 @@ HexagonII::CompoundGroup HexagonInstrInf
case Hexagon::C2_cmpeq:
case Hexagon::C2_cmpgt:
case Hexagon::C2_cmpgtu:
- DstReg = MI->getOperand(0).getReg();
- Src1Reg = MI->getOperand(1).getReg();
- Src2Reg = MI->getOperand(2).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ Src1Reg = MI.getOperand(1).getReg();
+ Src2Reg = MI.getOperand(2).getReg();
if (Hexagon::PredRegsRegClass.contains(DstReg) &&
(Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
@@ -3360,19 +3337,19 @@ HexagonII::CompoundGroup HexagonInstrInf
case Hexagon::C2_cmpgti:
case Hexagon::C2_cmpgtui:
// P0 = cmp.eq(Rs,#u2)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (Hexagon::PredRegsRegClass.contains(DstReg) &&
(Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
- isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
- ((isUInt<5>(MI->getOperand(2).getImm())) ||
- (MI->getOperand(2).getImm() == -1)))
+ isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
+ ((isUInt<5>(MI.getOperand(2).getImm())) ||
+ (MI.getOperand(2).getImm() == -1)))
return HexagonII::HCG_A;
break;
case Hexagon::A2_tfr:
// Rd = Rs
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
return HexagonII::HCG_A;
break;
@@ -3380,17 +3357,17 @@ HexagonII::CompoundGroup HexagonInstrInf
// Rd = #u6
// Do not test for #u6 size since the const is getting extended
// regardless and compound could be formed.
- DstReg = MI->getOperand(0).getReg();
+ DstReg = MI.getOperand(0).getReg();
if (isIntRegForSubInst(DstReg))
return HexagonII::HCG_A;
break;
case Hexagon::S2_tstbit_i:
- DstReg = MI->getOperand(0).getReg();
- Src1Reg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ Src1Reg = MI.getOperand(1).getReg();
if (Hexagon::PredRegsRegClass.contains(DstReg) &&
(Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
- MI->getOperand(2).isImm() &&
- isIntRegForSubInst(Src1Reg) && (MI->getOperand(2).getImm() == 0))
+ MI.getOperand(2).isImm() &&
+ isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
return HexagonII::HCG_A;
break;
// The fact that .new form is used pretty much guarantees
@@ -3401,7 +3378,7 @@ HexagonII::CompoundGroup HexagonInstrInf
case Hexagon::J2_jumpfnew:
case Hexagon::J2_jumptnewpt:
case Hexagon::J2_jumpfnewpt:
- Src1Reg = MI->getOperand(0).getReg();
+ Src1Reg = MI.getOperand(0).getReg();
if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
(Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
return HexagonII::HCG_B;
@@ -3421,15 +3398,15 @@ HexagonII::CompoundGroup HexagonInstrInf
// Returns -1 when there is no opcode found.
-unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr *GA,
- const MachineInstr *GB) const {
+unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
+ const MachineInstr &GB) const {
assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
- if ((GA->getOpcode() != Hexagon::C2_cmpeqi) ||
- (GB->getOpcode() != Hexagon::J2_jumptnew))
+ if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
+ (GB.getOpcode() != Hexagon::J2_jumptnew))
return -1;
- unsigned DestReg = GA->getOperand(0).getReg();
- if (!GB->readsRegister(DestReg))
+ unsigned DestReg = GA.getOperand(0).getReg();
+ if (!GB.readsRegister(DestReg))
return -1;
if (DestReg == Hexagon::P0)
return Hexagon::J4_cmpeqi_tp0_jump_nt;
@@ -3460,8 +3437,8 @@ int HexagonInstrInfo::getCondOpcode(int
// Return the cur value instruction for a given store.
-int HexagonInstrInfo::getDotCurOp(const MachineInstr* MI) const {
- switch (MI->getOpcode()) {
+int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
default: llvm_unreachable("Unknown .cur type");
case Hexagon::V6_vL32b_pi:
return Hexagon::V6_vL32b_cur_pi;
@@ -3559,12 +3536,12 @@ int HexagonInstrInfo::getDotCurOp(const
// Return the new value instruction for a given store.
-int HexagonInstrInfo::getDotNewOp(const MachineInstr* MI) const {
- int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
+int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
+ int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
if (NVOpcode >= 0) // Valid new-value store instruction.
return NVOpcode;
- switch (MI->getOpcode()) {
+ switch (MI.getOpcode()) {
default: llvm_unreachable("Unknown .new type");
case Hexagon::S4_storerb_ur:
return Hexagon::S4_storerbnew_ur;
@@ -3604,19 +3581,19 @@ int HexagonInstrInfo::getDotNewOp(const
// Returns the opcode to use when converting MI, which is a conditional jump,
// into a conditional instruction which uses the .new value of the predicate.
// We also use branch probabilities to add a hint to the jump.
-int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr *MI,
+int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
const MachineBranchProbabilityInfo *MBPI) const {
// We assume that block can have at most two successors.
bool taken = false;
- const MachineBasicBlock *Src = MI->getParent();
- const MachineOperand *BrTarget = &MI->getOperand(1);
- const MachineBasicBlock *Dst = BrTarget->getMBB();
+ const MachineBasicBlock *Src = MI.getParent();
+ const MachineOperand &BrTarget = MI.getOperand(1);
+ const MachineBasicBlock *Dst = BrTarget.getMBB();
const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
if (Prediction >= BranchProbability(1,2))
taken = true;
- switch (MI->getOpcode()) {
+ switch (MI.getOpcode()) {
case Hexagon::J2_jumpt:
return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
case Hexagon::J2_jumpf:
@@ -3629,13 +3606,13 @@ int HexagonInstrInfo::getDotNewPredJumpO
// Return .new predicate version for an instruction.
-int HexagonInstrInfo::getDotNewPredOp(const MachineInstr *MI,
+int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
const MachineBranchProbabilityInfo *MBPI) const {
- int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
+ int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
if (NewOpcode >= 0) // Valid predicate new instruction
return NewOpcode;
- switch (MI->getOpcode()) {
+ switch (MI.getOpcode()) {
// Condtional Jumps
case Hexagon::J2_jumpt:
case Hexagon::J2_jumpf:
@@ -3667,11 +3644,11 @@ int HexagonInstrInfo::getDotOldOp(const
// See if instruction could potentially be a duplex candidate.
// If so, return its group. Zero otherwise.
HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
- const MachineInstr *MI) const {
+ const MachineInstr &MI) const {
unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
auto &HRI = getRegisterInfo();
- switch (MI->getOpcode()) {
+ switch (MI.getOpcode()) {
default:
return HexagonII::HSIG_None;
//
@@ -3680,29 +3657,29 @@ HexagonII::SubInstructionGroup HexagonIn
// Rd = memw(Rs+#u4:2)
// Rd = memub(Rs+#u4:0)
case Hexagon::L2_loadri_io:
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
// Special case this one from Group L2.
// Rd = memw(r29+#u5:2)
if (isIntRegForSubInst(DstReg)) {
if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
HRI.getStackRegister() == SrcReg &&
- MI->getOperand(2).isImm() &&
- isShiftedUInt<5,2>(MI->getOperand(2).getImm()))
+ MI.getOperand(2).isImm() &&
+ isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_L2;
// Rd = memw(Rs+#u4:2)
if (isIntRegForSubInst(SrcReg) &&
- (MI->getOperand(2).isImm() &&
- isShiftedUInt<4,2>(MI->getOperand(2).getImm())))
+ (MI.getOperand(2).isImm() &&
+ isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
return HexagonII::HSIG_L1;
}
break;
case Hexagon::L2_loadrub_io:
// Rd = memub(Rs+#u4:0)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
- MI->getOperand(2).isImm() && isUInt<4>(MI->getOperand(2).getImm()))
+ MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_L1;
break;
//
@@ -3718,31 +3695,31 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadruh_io:
// Rd = memh/memuh(Rs+#u3:1)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
- MI->getOperand(2).isImm() &&
- isShiftedUInt<3,1>(MI->getOperand(2).getImm()))
+ MI.getOperand(2).isImm() &&
+ isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_L2;
break;
case Hexagon::L2_loadrb_io:
// Rd = memb(Rs+#u3:0)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
- MI->getOperand(2).isImm() &&
- isUInt<3>(MI->getOperand(2).getImm()))
+ MI.getOperand(2).isImm() &&
+ isUInt<3>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_L2;
break;
case Hexagon::L2_loadrd_io:
// Rdd = memd(r29+#u5:3)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isDblRegForSubInst(DstReg, HRI) &&
Hexagon::IntRegsRegClass.contains(SrcReg) &&
HRI.getStackRegister() == SrcReg &&
- MI->getOperand(2).isImm() &&
- isShiftedUInt<5,3>(MI->getOperand(2).getImm()))
+ MI.getOperand(2).isImm() &&
+ isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_L2;
break;
// dealloc_return is not documented in Hexagon Manual, but marked
@@ -3755,7 +3732,7 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::JMPret :
// jumpr r31
// Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
- DstReg = MI->getOperand(0).getReg();
+ DstReg = MI.getOperand(0).getReg();
if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
return HexagonII::HSIG_L2;
break;
@@ -3765,8 +3742,8 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::JMPretfnewpt :
case Hexagon::JMPrettnew :
case Hexagon::JMPretfnew :
- DstReg = MI->getOperand(1).getReg();
- SrcReg = MI->getOperand(0).getReg();
+ DstReg = MI.getOperand(1).getReg();
+ SrcReg = MI.getOperand(0).getReg();
// [if ([!]p0[.new])] jumpr r31
if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
(Hexagon::P0 == SrcReg)) &&
@@ -3780,7 +3757,7 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::L4_return_tnew_pt :
case Hexagon::L4_return_fnew_pt :
// [if ([!]p0[.new])] dealloc_return
- SrcReg = MI->getOperand(0).getReg();
+ SrcReg = MI.getOperand(0).getReg();
if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
return HexagonII::HSIG_L2;
break;
@@ -3792,25 +3769,25 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::S2_storeri_io:
// Special case this one from Group S2.
// memw(r29+#u5:2) = Rt
- Src1Reg = MI->getOperand(0).getReg();
- Src2Reg = MI->getOperand(2).getReg();
+ Src1Reg = MI.getOperand(0).getReg();
+ Src2Reg = MI.getOperand(2).getReg();
if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
isIntRegForSubInst(Src2Reg) &&
- HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
- isShiftedUInt<5,2>(MI->getOperand(1).getImm()))
+ HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
+ isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
return HexagonII::HSIG_S2;
// memw(Rs+#u4:2) = Rt
if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
- MI->getOperand(1).isImm() &&
- isShiftedUInt<4,2>(MI->getOperand(1).getImm()))
+ MI.getOperand(1).isImm() &&
+ isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
return HexagonII::HSIG_S1;
break;
case Hexagon::S2_storerb_io:
// memb(Rs+#u4:0) = Rt
- Src1Reg = MI->getOperand(0).getReg();
- Src2Reg = MI->getOperand(2).getReg();
+ Src1Reg = MI.getOperand(0).getReg();
+ Src2Reg = MI.getOperand(2).getReg();
if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
- MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()))
+ MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
return HexagonII::HSIG_S1;
break;
//
@@ -3824,42 +3801,42 @@ HexagonII::SubInstructionGroup HexagonIn
// allocframe(#u5:3)
case Hexagon::S2_storerh_io:
// memh(Rs+#u3:1) = Rt
- Src1Reg = MI->getOperand(0).getReg();
- Src2Reg = MI->getOperand(2).getReg();
+ Src1Reg = MI.getOperand(0).getReg();
+ Src2Reg = MI.getOperand(2).getReg();
if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
- MI->getOperand(1).isImm() &&
- isShiftedUInt<3,1>(MI->getOperand(1).getImm()))
+ MI.getOperand(1).isImm() &&
+ isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
return HexagonII::HSIG_S1;
break;
case Hexagon::S2_storerd_io:
// memd(r29+#s6:3) = Rtt
- Src1Reg = MI->getOperand(0).getReg();
- Src2Reg = MI->getOperand(2).getReg();
+ Src1Reg = MI.getOperand(0).getReg();
+ Src2Reg = MI.getOperand(2).getReg();
if (isDblRegForSubInst(Src2Reg, HRI) &&
Hexagon::IntRegsRegClass.contains(Src1Reg) &&
- HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
- isShiftedInt<6,3>(MI->getOperand(1).getImm()))
+ HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
+ isShiftedInt<6,3>(MI.getOperand(1).getImm()))
return HexagonII::HSIG_S2;
break;
case Hexagon::S4_storeiri_io:
// memw(Rs+#u4:2) = #U1
- Src1Reg = MI->getOperand(0).getReg();
- if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
- isShiftedUInt<4,2>(MI->getOperand(1).getImm()) &&
- MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
+ Src1Reg = MI.getOperand(0).getReg();
+ if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
+ isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
+ MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_S2;
break;
case Hexagon::S4_storeirb_io:
// memb(Rs+#u4) = #U1
- Src1Reg = MI->getOperand(0).getReg();
+ Src1Reg = MI.getOperand(0).getReg();
if (isIntRegForSubInst(Src1Reg) &&
- MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()) &&
- MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
+ MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
+ MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_S2;
break;
case Hexagon::S2_allocframe:
- if (MI->getOperand(0).isImm() &&
- isShiftedUInt<5,3>(MI->getOperand(0).getImm()))
+ if (MI.getOperand(0).isImm() &&
+ isShiftedUInt<5,3>(MI.getOperand(0).getImm()))
return HexagonII::HSIG_S1;
break;
//
@@ -3881,31 +3858,31 @@ HexagonII::SubInstructionGroup HexagonIn
// Rd = sxth/sxtb/zxtb/zxth(Rs)
// Rd = and(Rs,#1)
case Hexagon::A2_addi:
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg)) {
// Rd = add(r29,#u6:2)
if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
- HRI.getStackRegister() == SrcReg && MI->getOperand(2).isImm() &&
- isShiftedUInt<6,2>(MI->getOperand(2).getImm()))
+ HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
+ isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_A;
// Rx = add(Rx,#s7)
- if ((DstReg == SrcReg) && MI->getOperand(2).isImm() &&
- isInt<7>(MI->getOperand(2).getImm()))
+ if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
+ isInt<7>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_A;
// Rd = add(Rs,#1)
// Rd = add(Rs,#-1)
- if (isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
- ((MI->getOperand(2).getImm() == 1) ||
- (MI->getOperand(2).getImm() == -1)))
+ if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
+ ((MI.getOperand(2).getImm() == 1) ||
+ (MI.getOperand(2).getImm() == -1)))
return HexagonII::HSIG_A;
}
break;
case Hexagon::A2_add:
// Rx = add(Rx,Rs)
- DstReg = MI->getOperand(0).getReg();
- Src1Reg = MI->getOperand(1).getReg();
- Src2Reg = MI->getOperand(2).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ Src1Reg = MI.getOperand(1).getReg();
+ Src2Reg = MI.getOperand(2).getReg();
if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
isIntRegForSubInst(Src2Reg))
return HexagonII::HSIG_A;
@@ -3914,18 +3891,18 @@ HexagonII::SubInstructionGroup HexagonIn
// Same as zxtb.
// Rd16=and(Rs16,#255)
// Rd16=and(Rs16,#1)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
- MI->getOperand(2).isImm() &&
- ((MI->getOperand(2).getImm() == 1) ||
- (MI->getOperand(2).getImm() == 255)))
+ MI.getOperand(2).isImm() &&
+ ((MI.getOperand(2).getImm() == 1) ||
+ (MI.getOperand(2).getImm() == 255)))
return HexagonII::HSIG_A;
break;
case Hexagon::A2_tfr:
// Rd = Rs
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
return HexagonII::HSIG_A;
break;
@@ -3934,7 +3911,7 @@ HexagonII::SubInstructionGroup HexagonIn
// Do not test for #u6 size since the const is getting extended
// regardless and compound could be formed.
// Rd = #-1
- DstReg = MI->getOperand(0).getReg();
+ DstReg = MI.getOperand(0).getReg();
if (isIntRegForSubInst(DstReg))
return HexagonII::HSIG_A;
break;
@@ -3945,51 +3922,51 @@ HexagonII::SubInstructionGroup HexagonIn
// if ([!]P0[.new]) Rd = #0
// Actual form:
// %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) &&
Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
- MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
+ MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
return HexagonII::HSIG_A;
break;
case Hexagon::C2_cmpeqi:
// P0 = cmp.eq(Rs,#u2)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (Hexagon::PredRegsRegClass.contains(DstReg) &&
Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
- MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm()))
+ MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
return HexagonII::HSIG_A;
break;
case Hexagon::A2_combineii:
case Hexagon::A4_combineii:
// Rdd = combine(#u2,#U2)
- DstReg = MI->getOperand(0).getReg();
+ DstReg = MI.getOperand(0).getReg();
if (isDblRegForSubInst(DstReg, HRI) &&
- ((MI->getOperand(1).isImm() && isUInt<2>(MI->getOperand(1).getImm())) ||
- (MI->getOperand(1).isGlobal() &&
- isUInt<2>(MI->getOperand(1).getOffset()))) &&
- ((MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm())) ||
- (MI->getOperand(2).isGlobal() &&
- isUInt<2>(MI->getOperand(2).getOffset()))))
+ ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
+ (MI.getOperand(1).isGlobal() &&
+ isUInt<2>(MI.getOperand(1).getOffset()))) &&
+ ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
+ (MI.getOperand(2).isGlobal() &&
+ isUInt<2>(MI.getOperand(2).getOffset()))))
return HexagonII::HSIG_A;
break;
case Hexagon::A4_combineri:
// Rdd = combine(Rs,#0)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
- ((MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) ||
- (MI->getOperand(2).isGlobal() && MI->getOperand(2).getOffset() == 0)))
+ ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
+ (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
return HexagonII::HSIG_A;
break;
case Hexagon::A4_combineir:
// Rdd = combine(#0,Rs)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(2).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(2).getReg();
if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
- ((MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) ||
- (MI->getOperand(1).isGlobal() && MI->getOperand(1).getOffset() == 0)))
+ ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
+ (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
return HexagonII::HSIG_A;
break;
case Hexagon::A2_sxtb:
@@ -3997,8 +3974,8 @@ HexagonII::SubInstructionGroup HexagonIn
case Hexagon::A2_zxtb:
case Hexagon::A2_zxth:
// Rd = sxth/sxtb/zxtb/zxth(Rs)
- DstReg = MI->getOperand(0).getReg();
- SrcReg = MI->getOperand(1).getReg();
+ DstReg = MI.getOperand(0).getReg();
+ SrcReg = MI.getOperand(1).getReg();
if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
return HexagonII::HSIG_A;
break;
@@ -4008,8 +3985,8 @@ HexagonII::SubInstructionGroup HexagonIn
}
-short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr *MI) const {
- return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Real);
+short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
+ return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
}
@@ -4017,30 +3994,30 @@ short HexagonInstrInfo::getEquivalentHWI
MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB)
const {
for (auto MII = BB->instr_begin(), End = BB->instr_end(); MII != End; MII++) {
- MachineInstr *MI = &*MII;
- if (MI->isDebugValue())
+ MachineInstr &MI = *MII;
+ if (MI.isDebugValue())
continue;
- return MI;
+ return &MI;
}
return nullptr;
}
unsigned HexagonInstrInfo::getInstrTimingClassLatency(
- const InstrItineraryData *ItinData, const MachineInstr *MI) const {
+ const InstrItineraryData *ItinData, const MachineInstr &MI) const {
// Default to one cycle for no itinerary. However, an "empty" itinerary may
// still have a MinLatency property, which getStageLatency checks.
if (!ItinData)
- return getInstrLatency(ItinData, *MI);
+ return getInstrLatency(ItinData, MI);
// Get the latency embedded in the itinerary. If we're not using timing class
// latencies or if we using BSB scheduling, then restrict the maximum latency
// to 1 (that is, either 0 or 1).
- if (MI->isTransient())
+ if (MI.isTransient())
return 0;
- unsigned Latency = ItinData->getStageLatency(MI->getDesc().getSchedClass());
+ unsigned Latency = ItinData->getStageLatency(MI.getDesc().getSchedClass());
if (!EnableTimingClassLatency ||
- MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>().
+ MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>().
useBSBScheduling())
if (Latency > 1)
Latency = 1;
@@ -4073,8 +4050,8 @@ unsigned HexagonInstrInfo::getInvertedPr
// Returns the max value that doesn't need to be extended.
-int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
& HexagonII::ExtentSignedMask;
unsigned bits = (F >> HexagonII::ExtentBitsPos)
@@ -4087,15 +4064,15 @@ int HexagonInstrInfo::getMaxValue(const
}
-unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr* MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
}
// Returns the min value that doesn't need to be extended.
-int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
& HexagonII::ExtentSignedMask;
unsigned bits = (F >> HexagonII::ExtentBitsPos)
@@ -4109,22 +4086,22 @@ int HexagonInstrInfo::getMinValue(const
// Returns opcode of the non-extended equivalent instruction.
-short HexagonInstrInfo::getNonExtOpcode(const MachineInstr *MI) const {
+short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
// Check if the instruction has a register form that uses register in place
// of the extended operand, if so return that as the non-extended form.
- short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
+ short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
if (NonExtOpcode >= 0)
return NonExtOpcode;
- if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
+ if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
// Check addressing mode and retrieve non-ext equivalent instruction.
switch (getAddrMode(MI)) {
case HexagonII::Absolute :
- return Hexagon::getBaseWithImmOffset(MI->getOpcode());
+ return Hexagon::getBaseWithImmOffset(MI.getOpcode());
case HexagonII::BaseImmOffset :
- return Hexagon::getBaseWithRegOffset(MI->getOpcode());
+ return Hexagon::getBaseWithRegOffset(MI.getOpcode());
case HexagonII::BaseLongOffset:
- return Hexagon::getRegShlForm(MI->getOpcode());
+ return Hexagon::getRegShlForm(MI.getOpcode());
default:
return -1;
@@ -4155,13 +4132,13 @@ bool HexagonInstrInfo::getPredReg(ArrayR
}
-short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr *MI) const {
- return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Pseudo);
+short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
+ return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
}
-short HexagonInstrInfo::getRegForm(const MachineInstr *MI) const {
- return Hexagon::getRegForm(MI->getOpcode());
+short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
+ return Hexagon::getRegForm(MI.getOpcode());
}
@@ -4169,11 +4146,11 @@ short HexagonInstrInfo::getRegForm(const
// Hexagon instructions are fixed length, 4 bytes, unless they
// use a constant extender, which requires another 4 bytes.
// For debug instructions and prolog labels, return 0.
-unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
- if (MI->isDebugValue() || MI->isPosition())
+unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
+ if (MI.isDebugValue() || MI.isPosition())
return 0;
- unsigned Size = MI->getDesc().getSize();
+ unsigned Size = MI.getDesc().getSize();
if (!Size)
// Assume the default insn size in case it cannot be determined
// for whatever reason.
@@ -4183,20 +4160,20 @@ unsigned HexagonInstrInfo::getSize(const
Size += HEXAGON_INSTR_SIZE;
// Try and compute number of instructions in asm.
- if (BranchRelaxAsmLarge && MI->getOpcode() == Hexagon::INLINEASM) {
- const MachineBasicBlock &MBB = *MI->getParent();
+ if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
+ const MachineBasicBlock &MBB = *MI.getParent();
const MachineFunction *MF = MBB.getParent();
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
// Count the number of register definitions to find the asm string.
unsigned NumDefs = 0;
- for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
+ for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
++NumDefs)
- assert(NumDefs != MI->getNumOperands()-2 && "No asm string?");
+ assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
- assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?");
+ assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
// Disassemble the AsmStr and approximate number of instructions.
- const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
+ const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
Size = getInlineAsmLength(AsmStr, *MAI);
}
@@ -4204,16 +4181,16 @@ unsigned HexagonInstrInfo::getSize(const
}
-uint64_t HexagonInstrInfo::getType(const MachineInstr* MI) const {
- const uint64_t F = MI->getDesc().TSFlags;
+uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
+ const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
}
-unsigned HexagonInstrInfo::getUnits(const MachineInstr* MI) const {
- const TargetSubtargetInfo &ST = MI->getParent()->getParent()->getSubtarget();
+unsigned HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
+ const TargetSubtargetInfo &ST = MI.getParent()->getParent()->getSubtarget();
const InstrItineraryData &II = *ST.getInstrItineraryData();
- const InstrStage &IS = *II.beginStage(MI->getDesc().getSchedClass());
+ const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
return IS.getUnits();
}
@@ -4242,12 +4219,12 @@ unsigned HexagonInstrInfo::nonDbgBundleS
/// immediateExtend - Changes the instruction in place to one using an immediate
/// extender.
-void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
+void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
assert((isExtendable(MI)||isConstExtended(MI)) &&
"Instruction must be extendable");
// Find which operand is extendable.
short ExtOpNum = getCExtOpNum(MI);
- MachineOperand &MO = MI->getOperand(ExtOpNum);
+ MachineOperand &MO = MI.getOperand(ExtOpNum);
// This needs to be something we understand.
assert((MO.isMBB() || MO.isImm()) &&
"Branch with unknown extendable field type");
@@ -4257,22 +4234,22 @@ void HexagonInstrInfo::immediateExtend(M
bool HexagonInstrInfo::invertAndChangeJumpTarget(
- MachineInstr* MI, MachineBasicBlock* NewTarget) const {
+ MachineInstr &MI, MachineBasicBlock *NewTarget) const {
DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
- << NewTarget->getNumber(); MI->dump(););
- assert(MI->isBranch());
- unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode());
- int TargetPos = MI->getNumOperands() - 1;
+ << NewTarget->getNumber(); MI.dump(););
+ assert(MI.isBranch());
+ unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
+ int TargetPos = MI.getNumOperands() - 1;
// In general branch target is the last operand,
// but some implicit defs added at the end might change it.
- while ((TargetPos > -1) && !MI->getOperand(TargetPos).isMBB())
+ while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
--TargetPos;
- assert((TargetPos >= 0) && MI->getOperand(TargetPos).isMBB());
- MI->getOperand(TargetPos).setMBB(NewTarget);
- if (EnableBranchPrediction && isPredicatedNew(*MI)) {
+ assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
+ MI.getOperand(TargetPos).setMBB(NewTarget);
+ if (EnableBranchPrediction && isPredicatedNew(MI)) {
NewOpcode = reversePrediction(NewOpcode);
}
- MI->setDesc(get(NewOpcode));
+ MI.setDesc(get(NewOpcode));
return true;
}
@@ -4282,13 +4259,12 @@ void HexagonInstrInfo::genAllInsnTimingC
MachineFunction::iterator A = MF.begin();
MachineBasicBlock &B = *A;
MachineBasicBlock::iterator I = B.begin();
- MachineInstr *MI = &*I;
- DebugLoc DL = MI->getDebugLoc();
+ DebugLoc DL = I->getDebugLoc();
MachineInstr *NewMI;
for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
- NewMI = BuildMI(B, MI, DL, get(insn));
+ NewMI = BuildMI(B, I, DL, get(insn));
DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
" Class: " << NewMI->getDesc().getSchedClass());
NewMI->eraseFromParent();
@@ -4300,9 +4276,9 @@ void HexagonInstrInfo::genAllInsnTimingC
// inverts the predication logic.
// p -> NotP
// NotP -> P
-bool HexagonInstrInfo::reversePredSense(MachineInstr* MI) const {
- DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI->dump());
- MI->setDesc(get(getInvertedPredicatedOpcode(MI->getOpcode())));
+bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
+ DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
+ MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
return true;
}
@@ -4326,6 +4302,6 @@ bool HexagonInstrInfo::validateBranchCon
}
-short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr *MI) const {
- return Hexagon::xformRegToImmOffset(MI->getOpcode());
+short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr &MI) const {
+ return Hexagon::xformRegToImmOffset(MI.getOpcode());
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Fri Jul 29 16:49:42 2016
@@ -205,6 +205,9 @@ public:
/// Returns true if the instruction is already predicated.
bool isPredicated(const MachineInstr &MI) const override;
+ /// Return true for post-incremented instructions.
+ bool isPostIncrement(const MachineInstr *MI) const override;
+
/// Convert the instruction into a predicated instruction.
/// It returns true if the operation was successful.
bool PredicateInstruction(MachineInstr &MI,
@@ -284,49 +287,48 @@ public:
unsigned createVR(MachineFunction* MF, MVT VT) const;
- bool isAbsoluteSet(const MachineInstr* MI) const;
- bool isAccumulator(const MachineInstr *MI) const;
- bool isComplex(const MachineInstr *MI) const;
- bool isCompoundBranchInstr(const MachineInstr *MI) const;
- bool isCondInst(const MachineInstr *MI) const;
- bool isConditionalALU32 (const MachineInstr* MI) const;
- bool isConditionalLoad(const MachineInstr* MI) const;
- bool isConditionalStore(const MachineInstr* MI) const;
- bool isConditionalTransfer(const MachineInstr* MI) const;
- bool isConstExtended(const MachineInstr *MI) const;
- bool isDeallocRet(const MachineInstr *MI) const;
- bool isDependent(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) const;
- bool isDotCurInst(const MachineInstr* MI) const;
- bool isDotNewInst(const MachineInstr* MI) const;
- bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
- bool isEarlySourceInstr(const MachineInstr *MI) const;
+ bool isAbsoluteSet(const MachineInstr &MI) const;
+ bool isAccumulator(const MachineInstr &MI) const;
+ bool isComplex(const MachineInstr &MI) const;
+ bool isCompoundBranchInstr(const MachineInstr &MI) const;
+ bool isCondInst(const MachineInstr &MI) const;
+ bool isConditionalALU32 (const MachineInstr &MI) const;
+ bool isConditionalLoad(const MachineInstr &MI) const;
+ bool isConditionalStore(const MachineInstr &MI) const;
+ bool isConditionalTransfer(const MachineInstr &MI) const;
+ bool isConstExtended(const MachineInstr &MI) const;
+ bool isDeallocRet(const MachineInstr &MI) const;
+ bool isDependent(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) const;
+ bool isDotCurInst(const MachineInstr &MI) const;
+ bool isDotNewInst(const MachineInstr &MI) const;
+ bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
+ bool isEarlySourceInstr(const MachineInstr &MI) const;
bool isEndLoopN(unsigned Opcode) const;
bool isExpr(unsigned OpType) const;
- bool isExtendable(const MachineInstr* MI) const;
- bool isExtended(const MachineInstr* MI) const;
- bool isFloat(const MachineInstr *MI) const;
- bool isHVXMemWithAIndirect(const MachineInstr *I,
- const MachineInstr *J) const;
- bool isIndirectCall(const MachineInstr *MI) const;
- bool isIndirectL4Return(const MachineInstr *MI) const;
- bool isJumpR(const MachineInstr *MI) const;
- bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const;
- bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
- const MachineInstr *ESMI) const;
- bool isLateResultInstr(const MachineInstr *MI) const;
- bool isLateSourceInstr(const MachineInstr *MI) const;
- bool isLoopN(const MachineInstr *MI) const;
- bool isMemOp(const MachineInstr *MI) const;
- bool isNewValue(const MachineInstr* MI) const;
+ bool isExtendable(const MachineInstr &MI) const;
+ bool isExtended(const MachineInstr &MI) const;
+ bool isFloat(const MachineInstr &MI) const;
+ bool isHVXMemWithAIndirect(const MachineInstr &I,
+ const MachineInstr &J) const;
+ bool isIndirectCall(const MachineInstr &MI) const;
+ bool isIndirectL4Return(const MachineInstr &MI) const;
+ bool isJumpR(const MachineInstr &MI) const;
+ bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
+ bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
+ const MachineInstr &ESMI) const;
+ bool isLateResultInstr(const MachineInstr &MI) const;
+ bool isLateSourceInstr(const MachineInstr &MI) const;
+ bool isLoopN(const MachineInstr &MI) const;
+ bool isMemOp(const MachineInstr &MI) const;
+ bool isNewValue(const MachineInstr &MI) const;
bool isNewValue(unsigned Opcode) const;
- bool isNewValueInst(const MachineInstr* MI) const;
- bool isNewValueJump(const MachineInstr* MI) const;
+ bool isNewValueInst(const MachineInstr &MI) const;
+ bool isNewValueJump(const MachineInstr &MI) const;
bool isNewValueJump(unsigned Opcode) const;
- bool isNewValueStore(const MachineInstr* MI) const;
+ bool isNewValueStore(const MachineInstr &MI) const;
bool isNewValueStore(unsigned Opcode) const;
- bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
- bool isPostIncrement(const MachineInstr* MI) const override;
+ bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
bool isPredicatedNew(const MachineInstr &MI) const;
bool isPredicatedNew(unsigned Opcode) const;
bool isPredicatedTrue(const MachineInstr &MI) const;
@@ -334,85 +336,85 @@ public:
bool isPredicated(unsigned Opcode) const;
bool isPredicateLate(unsigned Opcode) const;
bool isPredictedTaken(unsigned Opcode) const;
- bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
+ bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
bool isSignExtendingLoad(const MachineInstr &MI) const;
- bool isSolo(const MachineInstr* MI) const;
- bool isSpillPredRegOp(const MachineInstr *MI) const;
- bool isTailCall(const MachineInstr *MI) const;
- bool isTC1(const MachineInstr *MI) const;
- bool isTC2(const MachineInstr *MI) const;
- bool isTC2Early(const MachineInstr *MI) const;
- bool isTC4x(const MachineInstr *MI) const;
- bool isToBeScheduledASAP(const MachineInstr *MI1,
- const MachineInstr *MI2) const;
- bool isV60VectorInstruction(const MachineInstr *MI) const;
+ bool isSolo(const MachineInstr &MI) const;
+ bool isSpillPredRegOp(const MachineInstr &MI) const;
+ bool isTailCall(const MachineInstr &MI) const;
+ bool isTC1(const MachineInstr &MI) const;
+ bool isTC2(const MachineInstr &MI) const;
+ bool isTC2Early(const MachineInstr &MI) const;
+ bool isTC4x(const MachineInstr &MI) const;
+ bool isToBeScheduledASAP(const MachineInstr &MI1,
+ const MachineInstr &MI2) const;
+ bool isV60VectorInstruction(const MachineInstr &MI) const;
bool isValidAutoIncImm(const EVT VT, const int Offset) const;
bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
- bool isVecAcc(const MachineInstr *MI) const;
- bool isVecALU(const MachineInstr *MI) const;
- bool isVecUsableNextPacket(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) const;
+ bool isVecAcc(const MachineInstr &MI) const;
+ bool isVecALU(const MachineInstr &MI) const;
+ bool isVecUsableNextPacket(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) const;
bool isZeroExtendingLoad(const MachineInstr &MI) const;
- bool addLatencyToSchedule(const MachineInstr *MI1,
- const MachineInstr *MI2) const;
- bool canExecuteInBundle(const MachineInstr *First,
- const MachineInstr *Second) const;
+ bool addLatencyToSchedule(const MachineInstr &MI1,
+ const MachineInstr &MI2) const;
+ bool canExecuteInBundle(const MachineInstr &First,
+ const MachineInstr &Second) const;
bool hasEHLabel(const MachineBasicBlock *B) const;
- bool hasNonExtEquivalent(const MachineInstr *MI) const;
- bool hasPseudoInstrPair(const MachineInstr *MI) const;
+ bool hasNonExtEquivalent(const MachineInstr &MI) const;
+ bool hasPseudoInstrPair(const MachineInstr &MI) const;
bool hasUncondBranch(const MachineBasicBlock *B) const;
- bool mayBeCurLoad(const MachineInstr* MI) const;
- bool mayBeNewStore(const MachineInstr* MI) const;
- bool producesStall(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) const;
- bool producesStall(const MachineInstr *MI,
+ bool mayBeCurLoad(const MachineInstr &MI) const;
+ bool mayBeNewStore(const MachineInstr &MI) const;
+ bool producesStall(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) const;
+ bool producesStall(const MachineInstr &MI,
MachineBasicBlock::const_instr_iterator MII) const;
- bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
+ bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
bool PredOpcodeHasJMP_c(unsigned Opcode) const;
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
- short getAbsoluteForm(const MachineInstr *MI) const;
- unsigned getAddrMode(const MachineInstr* MI) const;
- unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
+ short getAbsoluteForm(const MachineInstr &MI) const;
+ unsigned getAddrMode(const MachineInstr &MI) const;
+ unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset,
unsigned &AccessSize) const;
short getBaseWithLongOffset(short Opcode) const;
- short getBaseWithLongOffset(const MachineInstr *MI) const;
- short getBaseWithRegOffset(const MachineInstr *MI) const;
+ short getBaseWithLongOffset(const MachineInstr &MI) const;
+ short getBaseWithRegOffset(const MachineInstr &MI) const;
SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
- unsigned getCExtOpNum(const MachineInstr *MI) const;
+ unsigned getCExtOpNum(const MachineInstr &MI) const;
HexagonII::CompoundGroup
- getCompoundCandidateGroup(const MachineInstr *MI) const;
- unsigned getCompoundOpcode(const MachineInstr *GA,
- const MachineInstr *GB) const;
+ getCompoundCandidateGroup(const MachineInstr &MI) const;
+ unsigned getCompoundOpcode(const MachineInstr &GA,
+ const MachineInstr &GB) const;
int getCondOpcode(int Opc, bool sense) const;
- int getDotCurOp(const MachineInstr* MI) const;
- int getDotNewOp(const MachineInstr* MI) const;
- int getDotNewPredJumpOp(const MachineInstr *MI,
+ int getDotCurOp(const MachineInstr &MI) const;
+ int getDotNewOp(const MachineInstr &MI) const;
+ int getDotNewPredJumpOp(const MachineInstr &MI,
const MachineBranchProbabilityInfo *MBPI) const;
- int getDotNewPredOp(const MachineInstr *MI,
+ int getDotNewPredOp(const MachineInstr &MI,
const MachineBranchProbabilityInfo *MBPI) const;
int getDotOldOp(const int opc) const;
- HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
+ HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
const;
- short getEquivalentHWInstr(const MachineInstr *MI) const;
+ short getEquivalentHWInstr(const MachineInstr &MI) const;
MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
- const MachineInstr *MI) const;
+ const MachineInstr &MI) const;
bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
unsigned getInvertedPredicatedOpcode(const int Opc) const;
- int getMaxValue(const MachineInstr *MI) const;
- unsigned getMemAccessSize(const MachineInstr* MI) const;
- int getMinValue(const MachineInstr *MI) const;
- short getNonExtOpcode(const MachineInstr *MI) const;
+ int getMaxValue(const MachineInstr &MI) const;
+ unsigned getMemAccessSize(const MachineInstr &MI) const;
+ int getMinValue(const MachineInstr &MI) const;
+ short getNonExtOpcode(const MachineInstr &MI) const;
bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
unsigned &PredRegPos, unsigned &PredRegFlags) const;
- short getPseudoInstrPair(const MachineInstr *MI) const;
- short getRegForm(const MachineInstr *MI) const;
- unsigned getSize(const MachineInstr *MI) const;
- uint64_t getType(const MachineInstr* MI) const;
- unsigned getUnits(const MachineInstr* MI) const;
+ short getPseudoInstrPair(const MachineInstr &MI) const;
+ short getRegForm(const MachineInstr &MI) const;
+ unsigned getSize(const MachineInstr &MI) const;
+ uint64_t getType(const MachineInstr &MI) const;
+ unsigned getUnits(const MachineInstr &MI) const;
unsigned getValidSubTargets(const unsigned Opcode) const;
@@ -422,14 +424,14 @@ public:
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
- void immediateExtend(MachineInstr *MI) const;
- bool invertAndChangeJumpTarget(MachineInstr* MI,
+ void immediateExtend(MachineInstr &MI) const;
+ bool invertAndChangeJumpTarget(MachineInstr &MI,
MachineBasicBlock* NewTarget) const;
void genAllInsnTimingClasses(MachineFunction &MF) const;
- bool reversePredSense(MachineInstr* MI) const;
+ bool reversePredSense(MachineInstr &MI) const;
unsigned reversePrediction(unsigned Opcode) const;
bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
- short xformRegToImmOffset(const MachineInstr *MI) const;
+ short xformRegToImmOffset(const MachineInstr &MI) const;
};
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp Fri Jul 29 16:49:42 2016
@@ -72,7 +72,7 @@ bool HexagonCallMutation::shouldTFRICall
return false;
// TypeXTYPE are 64 bit operations.
- if (HII.getType(Inst2.getInstr()) == HexagonII::TypeXTYPE)
+ if (HII.getType(*Inst2.getInstr()) == HexagonII::TypeXTYPE)
return true;
return false;
}
@@ -168,7 +168,7 @@ bool VLIWResourceModel::isResourceAvaila
continue;
// Enable .cur formation.
- if (QII.mayBeCurLoad(Packet[i]->getInstr()))
+ if (QII.mayBeCurLoad(*Packet[i]->getInstr()))
continue;
for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(),
@@ -616,7 +616,7 @@ int ConvergingVLIWScheduler::SchedulingC
if (!SU || SU->isScheduled)
return ResCount;
- MachineInstr *Instr = SU->getInstr();
+ MachineInstr &Instr = *SU->getInstr();
DEBUG(if (verbose) dbgs() << ((Q.getID() == TopQID) ? "(top|" : "(bot|"));
// Forced priority is high.
@@ -705,7 +705,7 @@ int ConvergingVLIWScheduler::SchedulingC
// available for it.
auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
auto &QII = *QST.getInstrInfo();
- if (SU->isInstr() && QII.mayBeCurLoad(SU->getInstr())) {
+ if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
if (Q.getID() == TopQID && Top.ResourceModel->isResourceAvailable(SU)) {
ResCount += PriorityTwo;
DEBUG(if (verbose) dbgs() << "C|");
@@ -744,11 +744,11 @@ int ConvergingVLIWScheduler::SchedulingC
// Check for stalls in the previous packet.
if (Q.getID() == TopQID) {
for (auto J : Top.ResourceModel->OldPacket)
- if (QII.producesStall(J->getInstr(), Instr))
+ if (QII.producesStall(*J->getInstr(), Instr))
ResCount -= PriorityOne;
} else {
for (auto J : Bot.ResourceModel->OldPacket)
- if (QII.producesStall(Instr, J->getInstr()))
+ if (QII.producesStall(Instr, *J->getInstr()))
ResCount -= PriorityOne;
}
}
@@ -841,8 +841,8 @@ pickNodeFromQueue(ReadyQueue &Q, const R
const MachineInstr *CandI = Candidate.SU->getInstr();
const InstrItineraryData *InstrItins = QST.getInstrItineraryData();
- unsigned InstrLatency = QII.getInstrTimingClassLatency(InstrItins, MI);
- unsigned CandLatency = QII.getInstrTimingClassLatency(InstrItins, CandI);
+ unsigned InstrLatency = QII.getInstrTimingClassLatency(InstrItins, *MI);
+ unsigned CandLatency = QII.getInstrTimingClassLatency(InstrItins, *CandI);
DEBUG(dbgs() << "TC Tie Breaker Cand: "
<< CandLatency << " Instr:" << InstrLatency << "\n"
<< *MI << *CandI << "\n");
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOptAddrMode.cpp Fri Jul 29 16:49:42 2016
@@ -79,12 +79,12 @@ private:
NodeAddr<UseNode *> UseN, unsigned UseMOnum);
bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
InstrEvalMap &InstrEvalResult, short &SizeInc);
- bool hasRepForm(MachineInstr *MI, unsigned TfrDefR);
- bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr *MI,
+ bool hasRepForm(MachineInstr &MI, unsigned TfrDefR);
+ bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr &MI,
const NodeList &UNodeList);
void getAllRealUses(NodeAddr<StmtNode *> SN, NodeList &UNodeList);
bool allValidCandidates(NodeAddr<StmtNode *> SA, NodeList &UNodeList);
- short getBaseWithLongOffset(const MachineInstr *MI) const;
+ short getBaseWithLongOffset(const MachineInstr &MI) const;
void updateMap(NodeAddr<InstrNode *> IA);
bool constructDefMap(MachineBasicBlock *B);
bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
@@ -104,14 +104,14 @@ INITIALIZE_PASS_DEPENDENCY(MachineDomina
INITIALIZE_PASS_END(HexagonOptAddrMode, "opt-amode", "Optimize addressing mode",
false, false)
-bool HexagonOptAddrMode::hasRepForm(MachineInstr *MI, unsigned TfrDefR) {
- const MCInstrDesc &MID = MI->getDesc();
+bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) {
+ const MCInstrDesc &MID = MI.getDesc();
- if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(*MI))
+ if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI))
return false;
if (MID.mayStore()) {
- MachineOperand StOp = MI->getOperand(MI->getNumOperands() - 1);
+ MachineOperand StOp = MI.getOperand(MI.getNumOperands() - 1);
if (StOp.isReg() && StOp.getReg() == TfrDefR)
return false;
}
@@ -137,14 +137,14 @@ bool HexagonOptAddrMode::hasRepForm(Mach
// Above three instructions can be replaced with Rd = memw(Rt<<#2 + ##foo+28)
bool HexagonOptAddrMode::canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN,
- MachineInstr *MI,
+ MachineInstr &MI,
const NodeList &UNodeList) {
// check offset size in addasl. if 'offset > 3' return false
- const MachineOperand &OffsetOp = MI->getOperand(3);
+ const MachineOperand &OffsetOp = MI.getOperand(3);
if (!OffsetOp.isImm() || OffsetOp.getImm() > 3)
return false;
- unsigned OffsetReg = MI->getOperand(2).getReg();
+ unsigned OffsetReg = MI.getOperand(2).getReg();
RegisterRef OffsetRR;
NodeId OffsetRegRD = 0;
for (NodeAddr<UseNode *> UA : AddAslSN.Addr->members_if(DFG->IsUse, *DFG)) {
@@ -162,25 +162,25 @@ bool HexagonOptAddrMode::canRemoveAddasl
RDefMap[OffsetRR][IA.Id] != OffsetRegRD)
return false;
- MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode();
+ MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode();
NodeAddr<DefNode *> OffsetRegDN = DFG->addr<DefNode *>(OffsetRegRD);
// Reaching Def to an offset register can't be a phi.
if ((OffsetRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
- MI->getParent() != UseMI->getParent())
+ MI.getParent() != UseMI.getParent())
return false;
- const MCInstrDesc &UseMID = UseMI->getDesc();
+ const MCInstrDesc &UseMID = UseMI.getDesc();
if ((!UseMID.mayLoad() && !UseMID.mayStore()) ||
HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
getBaseWithLongOffset(UseMI) < 0)
return false;
// Addasl output can't be a store value.
- if (UseMID.mayStore() && UseMI->getOperand(2).isReg() &&
- UseMI->getOperand(2).getReg() == MI->getOperand(0).getReg())
+ if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
+ UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
return false;
- for (auto &Mo : UseMI->operands())
+ for (auto &Mo : UseMI.operands())
if (Mo.isFI())
return false;
}
@@ -261,8 +261,8 @@ bool HexagonOptAddrMode::analyzeUses(uns
bool CanBeReplaced = false;
NodeAddr<UseNode *> UN = *I;
NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
- MachineInstr *MI = SN.Addr->getCode();
- const MCInstrDesc &MID = MI->getDesc();
+ MachineInstr &MI = *SN.Addr->getCode();
+ const MCInstrDesc &MID = MI.getDesc();
if ((MID.mayLoad() || MID.mayStore())) {
if (!hasRepForm(MI, tfrDefR)) {
KeepTfr = true;
@@ -270,10 +270,10 @@ bool HexagonOptAddrMode::analyzeUses(uns
}
SizeInc++;
CanBeReplaced = true;
- } else if (MI->getOpcode() == Hexagon::S2_addasl_rrri) {
+ } else if (MI.getOpcode() == Hexagon::S2_addasl_rrri) {
NodeList AddaslUseList;
- DEBUG(dbgs() << "\nGetting ReachedUses for === " << *MI << "\n");
+ DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n");
getAllRealUses(SN, AddaslUseList);
// Process phi nodes.
if (allValidCandidates(SN, AddaslUseList) &&
@@ -290,7 +290,7 @@ bool HexagonOptAddrMode::analyzeUses(uns
// M4_mpyrr_addr -> M4_mpyrr_addi
KeepTfr = true;
- InstrEvalResult[MI] = CanBeReplaced;
+ InstrEvalResult[&MI] = CanBeReplaced;
HasRepInstr |= CanBeReplaced;
}
@@ -313,8 +313,8 @@ bool HexagonOptAddrMode::changeLoad(Mach
MachineInstrBuilder MIB;
if (ImmOpNum == 1) {
- if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
- short NewOpCode = HII->getBaseWithLongOffset(OldMI);
+ if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
+ short NewOpCode = HII->getBaseWithLongOffset(*OldMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n");
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
MIB.addOperand(OldMI->getOperand(0));
@@ -323,8 +323,8 @@ bool HexagonOptAddrMode::changeLoad(Mach
MIB.addOperand(ImmOp);
OpStart = 4;
Changed = true;
- } else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
- short NewOpCode = HII->getAbsoluteForm(OldMI);
+ } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
+ short NewOpCode = HII->getAbsoluteForm(*OldMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n");
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
.addOperand(OldMI->getOperand(0));
@@ -340,7 +340,7 @@ bool HexagonOptAddrMode::changeLoad(Mach
DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
DEBUG(dbgs() << "[TO]: " << MIB << "\n");
} else if (ImmOpNum == 2 && OldMI->getOperand(3).getImm() == 0) {
- short NewOpCode = HII->xformRegToImmOffset(OldMI);
+ short NewOpCode = HII->xformRegToImmOffset(*OldMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n");
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
MIB.addOperand(OldMI->getOperand(0));
@@ -370,8 +370,8 @@ bool HexagonOptAddrMode::changeStore(Mac
++InsertPt;
MachineInstrBuilder MIB;
if (ImmOpNum == 0) {
- if (HII->getAddrMode(OldMI) == HexagonII::BaseRegOffset) {
- short NewOpCode = HII->getBaseWithLongOffset(OldMI);
+ if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
+ short NewOpCode = HII->getBaseWithLongOffset(*OldMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n");
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
MIB.addOperand(OldMI->getOperand(1));
@@ -379,8 +379,8 @@ bool HexagonOptAddrMode::changeStore(Mac
MIB.addOperand(ImmOp);
MIB.addOperand(OldMI->getOperand(3));
OpStart = 4;
- } else if (HII->getAddrMode(OldMI) == HexagonII::BaseImmOffset) {
- short NewOpCode = HII->getAbsoluteForm(OldMI);
+ } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
+ short NewOpCode = HII->getAbsoluteForm(*OldMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n");
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
const GlobalValue *GV = ImmOp.getGlobal();
@@ -393,7 +393,7 @@ bool HexagonOptAddrMode::changeStore(Mac
DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
DEBUG(dbgs() << "[TO]: " << MIB << "\n");
} else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
- short NewOpCode = HII->xformRegToImmOffset(OldMI);
+ short NewOpCode = HII->xformRegToImmOffset(*OldMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n");
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
MIB.addOperand(OldMI->getOperand(0));
@@ -411,7 +411,7 @@ bool HexagonOptAddrMode::changeStore(Mac
return Changed;
}
-short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr *MI) const {
+short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr &MI) const {
if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) {
short TempOpCode = HII->getBaseWithRegOffset(MI);
return HII->getBaseWithLongOffset(TempOpCode);
@@ -442,11 +442,11 @@ bool HexagonOptAddrMode::changeAddAsl(No
DEBUG(dbgs() << "[MI <BB#" << UseMI->getParent()->getNumber()
<< ">]: " << *UseMI << "\n");
const MCInstrDesc &UseMID = UseMI->getDesc();
- assert(HII->getAddrMode(UseMI) == HexagonII::BaseImmOffset);
+ assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset);
auto UsePos = MachineBasicBlock::iterator(UseMI);
MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
- short NewOpCode = getBaseWithLongOffset(UseMI);
+ short NewOpCode = getBaseWithLongOffset(*UseMI);
assert(NewOpCode >= 0 && "Invalid New opcode\n");
unsigned OpStart;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp Fri Jul 29 16:49:42 2016
@@ -202,11 +202,11 @@ bool HexagonDCE::rewrite(NodeAddr<InstrN
if (!getDFG().IsCode<NodeAttrs::Stmt>(IA))
return false;
DataFlowGraph &DFG = getDFG();
- MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
+ MachineInstr &MI = *NodeAddr<StmtNode*>(IA).Addr->getCode();
auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII());
if (HII.getAddrMode(MI) != HexagonII::PostInc)
return false;
- unsigned Opc = MI->getOpcode();
+ unsigned Opc = MI.getOpcode();
unsigned OpNum, NewOpc;
switch (Opc) {
case Hexagon::L2_loadri_pi:
@@ -240,7 +240,7 @@ bool HexagonDCE::rewrite(NodeAddr<InstrN
return getDeadNodes().count(DA.Id);
};
NodeList Defs;
- MachineOperand &Op = MI->getOperand(OpNum);
+ MachineOperand &Op = MI.getOperand(OpNum);
for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) {
if (&DA.Addr->getOp() != &Op)
continue;
@@ -255,12 +255,12 @@ bool HexagonDCE::rewrite(NodeAddr<InstrN
Remove.insert(D.Id);
if (trace())
- dbgs() << "Rewriting: " << *MI;
- MI->setDesc(HII.get(NewOpc));
- MI->getOperand(OpNum+2).setImm(0);
+ dbgs() << "Rewriting: " << MI;
+ MI.setDesc(HII.get(NewOpc));
+ MI.getOperand(OpNum+2).setImm(0);
removeOperand(IA, OpNum);
if (trace())
- dbgs() << " to: " << *MI;
+ dbgs() << " to: " << MI;
return true;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Fri Jul 29 16:49:42 2016
@@ -155,19 +155,19 @@ void HexagonSubtarget::HexagonDAGMutatio
// Update the latency of chain edges between v60 vector load or store
// instructions to be 1. These instructions cannot be scheduled in the
// same packet.
- MachineInstr *MI1 = SU.getInstr();
+ MachineInstr &MI1 = *SU.getInstr();
auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
- bool IsStoreMI1 = MI1->mayStore();
- bool IsLoadMI1 = MI1->mayLoad();
+ bool IsStoreMI1 = MI1.mayStore();
+ bool IsLoadMI1 = MI1.mayLoad();
if (!QII->isV60VectorInstruction(MI1) || !(IsStoreMI1 || IsLoadMI1))
continue;
for (auto &SI : SU.Succs) {
if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
continue;
- MachineInstr *MI2 = SI.getSUnit()->getInstr();
+ MachineInstr &MI2 = *SI.getSUnit()->getInstr();
if (!QII->isV60VectorInstruction(MI2))
continue;
- if ((IsStoreMI1 && MI2->mayStore()) || (IsLoadMI1 && MI2->mayLoad())) {
+ if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
SI.setLatency(1);
SU.setHeightDirty();
// Change the dependence in the opposite direction too.
@@ -203,8 +203,8 @@ bool HexagonSubtarget::enableSubRegLiven
}
// This helper function is responsible for increasing the latency only.
-void HexagonSubtarget::updateLatency(MachineInstr *SrcInst,
- MachineInstr *DstInst, SDep &Dep) const {
+void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
+ MachineInstr &DstInst, SDep &Dep) const {
if (!hasV60TOps())
return;
@@ -238,19 +238,19 @@ static SUnit *getZeroLatency(SUnit *N, S
/// Change the latency between the two SUnits.
void HexagonSubtarget::changeLatency(SUnit *Src, SmallVector<SDep, 4> &Deps,
SUnit *Dst, unsigned Lat) const {
- MachineInstr *SrcI = Src->getInstr();
+ MachineInstr &SrcI = *Src->getInstr();
for (auto &I : Deps) {
if (I.getSUnit() != Dst)
continue;
I.setLatency(Lat);
SUnit *UpdateDst = I.getSUnit();
- updateLatency(SrcI, UpdateDst->getInstr(), I);
+ updateLatency(SrcI, *UpdateDst->getInstr(), I);
// Update the latency of opposite edge too.
for (auto &PI : UpdateDst->Preds) {
if (PI.getSUnit() != Src || !PI.isAssignedRegDep())
continue;
PI.setLatency(Lat);
- updateLatency(SrcI, UpdateDst->getInstr(), PI);
+ updateLatency(SrcI, *UpdateDst->getInstr(), PI);
}
}
}
@@ -261,10 +261,10 @@ void HexagonSubtarget::changeLatency(SUn
// ther others, if needed.
bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
const HexagonInstrInfo *TII) const {
- MachineInstr *SrcInst = Src->getInstr();
- MachineInstr *DstInst = Dst->getInstr();
+ MachineInstr &SrcInst = *Src->getInstr();
+ MachineInstr &DstInst = *Dst->getInstr();
- if (SrcInst->isPHI() || DstInst->isPHI())
+ if (SrcInst.isPHI() || DstInst.isPHI())
return false;
// Check if the Dst instruction is the best candidate first.
@@ -301,9 +301,9 @@ bool HexagonSubtarget::isBestZeroLatency
// Update the latency of a Phi when the Phi bridges two instructions that
// require a multi-cycle latency.
-void HexagonSubtarget::changePhiLatency(MachineInstr *SrcInst, SUnit *Dst,
+void HexagonSubtarget::changePhiLatency(MachineInstr &SrcInst, SUnit *Dst,
SDep &Dep) const {
- if (!SrcInst->isPHI() || Dst->NumPreds == 0 || Dep.getLatency() != 0)
+ if (!SrcInst.isPHI() || Dst->NumPreds == 0 || Dep.getLatency() != 0)
return;
for (const SDep &PI : Dst->Preds) {
@@ -326,7 +326,7 @@ void HexagonSubtarget::adjustSchedDepend
const HexagonInstrInfo *QII = static_cast<const HexagonInstrInfo *>(getInstrInfo());
// Instructions with .new operands have zero latency.
- if (QII->canExecuteInBundle(SrcInst, DstInst) &&
+ if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
isBestZeroLatency(Src, Dst, QII)) {
Dep.setLatency(0);
return;
@@ -355,7 +355,7 @@ void HexagonSubtarget::adjustSchedDepend
// Check if we need to change any the latency values when Phis are added.
if (useBSBScheduling() && SrcInst->isPHI()) {
- changePhiLatency(SrcInst, Dst, Dep);
+ changePhiLatency(*SrcInst, Dst, Dep);
return;
}
@@ -365,13 +365,13 @@ void HexagonSubtarget::adjustSchedDepend
DstInst = Dst->Succs[0].getSUnit()->getInstr();
// Try to schedule uses near definitions to generate .cur.
- if (EnableDotCurSched && QII->isToBeScheduledASAP(SrcInst, DstInst) &&
+ if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
isBestZeroLatency(Src, Dst, QII)) {
Dep.setLatency(0);
return;
}
- updateLatency(SrcInst, DstInst, Dep);
+ updateLatency(*SrcInst, *DstInst, Dep);
}
unsigned HexagonSubtarget::getL1CacheLineSize() const {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Fri Jul 29 16:49:42 2016
@@ -139,13 +139,13 @@ public:
private:
// Helper function responsible for increasing the latency only.
- void updateLatency(MachineInstr *SrcInst, MachineInstr *DstInst, SDep &Dep)
+ void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
const;
void changeLatency(SUnit *Src, SmallVector<SDep, 4> &Deps, SUnit *Dst,
unsigned Lat) const;
bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII)
const;
- void changePhiLatency(MachineInstr *SrcInst, SUnit *Dst, SDep &Dep) const;
+ void changePhiLatency(MachineInstr &SrcInst, SUnit *Dst, SDep &Dep) const;
};
} // end namespace llvm
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Fri Jul 29 16:49:42 2016
@@ -126,7 +126,7 @@ static bool hasWriteToReadDep(const Mach
}
-static MachineBasicBlock::iterator moveInstrOut(MachineInstr *MI,
+static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI,
MachineBasicBlock::iterator BundleIt, bool Before) {
MachineBasicBlock::instr_iterator InsertPt;
if (Before)
@@ -134,20 +134,20 @@ static MachineBasicBlock::iterator moveI
else
InsertPt = std::next(BundleIt).getInstrIterator();
- MachineBasicBlock &B = *MI->getParent();
+ MachineBasicBlock &B = *MI.getParent();
// The instruction should at least be bundled with the preceding instruction
// (there will always be one, i.e. BUNDLE, if nothing else).
- assert(MI->isBundledWithPred());
- if (MI->isBundledWithSucc()) {
- MI->clearFlag(MachineInstr::BundledSucc);
- MI->clearFlag(MachineInstr::BundledPred);
+ assert(MI.isBundledWithPred());
+ if (MI.isBundledWithSucc()) {
+ MI.clearFlag(MachineInstr::BundledSucc);
+ MI.clearFlag(MachineInstr::BundledPred);
} else {
// If it's not bundled with the successor (i.e. it is the last one
// in the bundle), then we can simply unbundle it from the predecessor,
// which will take care of updating the predecessor's flag.
- MI->unbundleFromPred();
+ MI.unbundleFromPred();
}
- B.splice(InsertPt, &B, MI);
+ B.splice(InsertPt, &B, MI.getIterator());
// Get the size of the bundle without asserting.
MachineBasicBlock::const_instr_iterator I = BundleIt.getInstrIterator();
@@ -163,9 +163,9 @@ static MachineBasicBlock::iterator moveI
// Otherwise, extract the single instruction out and delete the bundle.
MachineBasicBlock::iterator NextIt = std::next(BundleIt);
- MachineInstr *SingleI = BundleIt->getNextNode();
- SingleI->unbundleFromPred();
- assert(!SingleI->isBundledWithSucc());
+ MachineInstr &SingleI = *BundleIt->getNextNode();
+ SingleI.unbundleFromPred();
+ assert(!SingleI.isBundledWithSucc());
BundleIt->eraseFromParent();
return NextIt;
}
@@ -266,7 +266,7 @@ bool HexagonPacketizerList::tryAllocateR
}
-bool HexagonPacketizerList::isCallDependent(const MachineInstr* MI,
+bool HexagonPacketizerList::isCallDependent(const MachineInstr &MI,
SDep::Kind DepType, unsigned DepReg) {
// Check for LR dependence.
if (DepReg == HRI->getRARegister())
@@ -283,7 +283,7 @@ bool HexagonPacketizerList::isCallDepend
// Assumes that the first operand of the CALLr is the function address.
if (HII->isIndirectCall(MI) && (DepType == SDep::Data)) {
- MachineOperand MO = MI->getOperand(0);
+ MachineOperand MO = MI.getOperand(0);
if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg))
return true;
}
@@ -296,29 +296,29 @@ static bool isRegDependence(const SDep::
DepType == SDep::Output;
}
-static bool isDirectJump(const MachineInstr* MI) {
- return MI->getOpcode() == Hexagon::J2_jump;
+static bool isDirectJump(const MachineInstr &MI) {
+ return MI.getOpcode() == Hexagon::J2_jump;
}
-static bool isSchedBarrier(const MachineInstr* MI) {
- switch (MI->getOpcode()) {
+static bool isSchedBarrier(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
case Hexagon::Y2_barrier:
return true;
}
return false;
}
-static bool isControlFlow(const MachineInstr* MI) {
- return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
+static bool isControlFlow(const MachineInstr &MI) {
+ return MI.getDesc().isTerminator() || MI.getDesc().isCall();
}
/// Returns true if the instruction modifies a callee-saved register.
-static bool doesModifyCalleeSavedReg(const MachineInstr *MI,
+static bool doesModifyCalleeSavedReg(const MachineInstr &MI,
const TargetRegisterInfo *TRI) {
- const MachineFunction &MF = *MI->getParent()->getParent();
+ const MachineFunction &MF = *MI.getParent()->getParent();
for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
- if (MI->modifiesRegister(*CSR, TRI))
+ if (MI.modifiesRegister(*CSR, TRI))
return true;
return false;
}
@@ -326,30 +326,30 @@ static bool doesModifyCalleeSavedReg(con
// TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
// Returns true if an instruction can be promoted to .new predicate or
// new-value store.
-bool HexagonPacketizerList::isNewifiable(const MachineInstr* MI,
+bool HexagonPacketizerList::isNewifiable(const MachineInstr &MI,
const TargetRegisterClass *NewRC) {
// Vector stores can be predicated, and can be new-value stores, but
// they cannot be predicated on a .new predicate value.
if (NewRC == &Hexagon::PredRegsRegClass)
- if (HII->isV60VectorInstruction(MI) && MI->mayStore())
+ if (HII->isV60VectorInstruction(MI) && MI.mayStore())
return false;
- return HII->isCondInst(MI) || MI->isReturn() || HII->mayBeNewStore(MI);
+ return HII->isCondInst(MI) || MI.isReturn() || HII->mayBeNewStore(MI);
}
// Promote an instructiont to its .cur form.
// At this time, we have already made a call to canPromoteToDotCur and made
// sure that it can *indeed* be promoted.
-bool HexagonPacketizerList::promoteToDotCur(MachineInstr* MI,
+bool HexagonPacketizerList::promoteToDotCur(MachineInstr &MI,
SDep::Kind DepType, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
assert(DepType == SDep::Data);
int CurOpcode = HII->getDotCurOp(MI);
- MI->setDesc(HII->get(CurOpcode));
+ MI.setDesc(HII->get(CurOpcode));
return true;
}
void HexagonPacketizerList::cleanUpDotCur() {
- MachineInstr *MI = NULL;
+ MachineInstr *MI = nullptr;
for (auto BI : CurrentPacketMIs) {
DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
if (BI->getOpcode() == Hexagon::V6_vL32b_cur_ai) {
@@ -370,12 +370,12 @@ void HexagonPacketizerList::cleanUpDotCu
}
// Check to see if an instruction can be dot cur.
-bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr *MI,
+bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
const TargetRegisterClass *RC) {
if (!HII->isV60VectorInstruction(MI))
return false;
- if (!HII->isV60VectorInstruction(&*MII))
+ if (!HII->isV60VectorInstruction(*MII))
return false;
// Already a dot new instruction.
@@ -391,14 +391,14 @@ bool HexagonPacketizerList::canPromoteTo
// Make sure candidate instruction uses cur.
DEBUG(dbgs() << "Can we DOT Cur Vector MI\n";
- MI->dump();
+ MI.dump();
dbgs() << "in packet\n";);
MachineInstr &MJ = *MII;
DEBUG({
dbgs() << "Checking CUR against ";
MJ.dump();
});
- unsigned DestReg = MI->getOperand(0).getReg();
+ unsigned DestReg = MI.getOperand(0).getReg();
bool FoundMatch = false;
for (auto &MO : MJ.operands())
if (MO.isReg() && MO.getReg() == DestReg)
@@ -414,7 +414,7 @@ bool HexagonPacketizerList::canPromoteTo
return false;
}
- DEBUG(dbgs() << "Can Dot CUR MI\n"; MI->dump(););
+ DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
// We can convert the opcode into a .cur.
return true;
}
@@ -422,7 +422,7 @@ bool HexagonPacketizerList::canPromoteTo
// Promote an instruction to its .new form. At this time, we have already
// made a call to canPromoteToDotNew and made sure that it can *indeed* be
// promoted.
-bool HexagonPacketizerList::promoteToDotNew(MachineInstr* MI,
+bool HexagonPacketizerList::promoteToDotNew(MachineInstr &MI,
SDep::Kind DepType, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
assert (DepType == SDep::Data);
@@ -431,18 +431,18 @@ bool HexagonPacketizerList::promoteToDot
NewOpcode = HII->getDotNewPredOp(MI, MBPI);
else
NewOpcode = HII->getDotNewOp(MI);
- MI->setDesc(HII->get(NewOpcode));
+ MI.setDesc(HII->get(NewOpcode));
return true;
}
-bool HexagonPacketizerList::demoteToDotOld(MachineInstr* MI) {
- int NewOpcode = HII->getDotOldOp(MI->getOpcode());
- MI->setDesc(HII->get(NewOpcode));
+bool HexagonPacketizerList::demoteToDotOld(MachineInstr &MI) {
+ int NewOpcode = HII->getDotOldOp(MI.getOpcode());
+ MI.setDesc(HII->get(NewOpcode));
return true;
}
-bool HexagonPacketizerList::useCallersSP(MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+bool HexagonPacketizerList::useCallersSP(MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::S2_storerd_io:
case Hexagon::S2_storeri_io:
@@ -453,7 +453,7 @@ bool HexagonPacketizerList::useCallersSP
llvm_unreachable("Unexpected instruction");
}
unsigned FrameSize = MF.getFrameInfo().getStackSize();
- MachineOperand &Off = MI->getOperand(1);
+ MachineOperand &Off = MI.getOperand(1);
int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
if (HII->isValidOffset(Opc, NewOff)) {
Off.setImm(NewOff);
@@ -462,8 +462,8 @@ bool HexagonPacketizerList::useCallersSP
return false;
}
-void HexagonPacketizerList::useCalleesSP(MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+void HexagonPacketizerList::useCalleesSP(MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::S2_storerd_io:
case Hexagon::S2_storeri_io:
@@ -474,7 +474,7 @@ void HexagonPacketizerList::useCalleesSP
llvm_unreachable("Unexpected instruction");
}
unsigned FrameSize = MF.getFrameInfo().getStackSize();
- MachineOperand &Off = MI->getOperand(1);
+ MachineOperand &Off = MI.getOperand(1);
Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
}
@@ -495,30 +495,30 @@ static PredicateKind getPredicateSense(c
return PK_False;
}
-static const MachineOperand &getPostIncrementOperand(const MachineInstr *MI,
+static const MachineOperand &getPostIncrementOperand(const MachineInstr &MI,
const HexagonInstrInfo *HII) {
- assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
+ assert(HII->isPostIncrement(&MI) && "Not a post increment operation.");
#ifndef NDEBUG
// Post Increment means duplicates. Use dense map to find duplicates in the
// list. Caution: Densemap initializes with the minimum of 64 buckets,
// whereas there are at most 5 operands in the post increment.
DenseSet<unsigned> DefRegsSet;
- for (auto &MO : MI->operands())
+ for (auto &MO : MI.operands())
if (MO.isReg() && MO.isDef())
DefRegsSet.insert(MO.getReg());
- for (auto &MO : MI->operands())
+ for (auto &MO : MI.operands())
if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
return MO;
#else
- if (MI->mayLoad()) {
- const MachineOperand &Op1 = MI->getOperand(1);
+ if (MI.mayLoad()) {
+ const MachineOperand &Op1 = MI.getOperand(1);
// The 2nd operand is always the post increment operand in load.
assert(Op1.isReg() && "Post increment operand has be to a register.");
return Op1;
}
- if (MI->getDesc().mayStore()) {
- const MachineOperand &Op0 = MI->getOperand(0);
+ if (MI.getDesc().mayStore()) {
+ const MachineOperand &Op0 = MI.getOperand(0);
// The 1st operand is always the post increment operand in store.
assert(Op0.isReg() && "Post increment operand has be to a register.");
return Op0;
@@ -529,13 +529,13 @@ static const MachineOperand &getPostIncr
}
// Get the value being stored.
-static const MachineOperand& getStoreValueOperand(const MachineInstr *MI) {
+static const MachineOperand& getStoreValueOperand(const MachineInstr &MI) {
// value being stored is always the last operand.
- return MI->getOperand(MI->getNumOperands()-1);
+ return MI.getOperand(MI.getNumOperands()-1);
}
-static bool isLoadAbsSet(const MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+static bool isLoadAbsSet(const MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::L4_loadrd_ap:
case Hexagon::L4_loadrb_ap:
@@ -548,9 +548,9 @@ static bool isLoadAbsSet(const MachineIn
return false;
}
-static const MachineOperand &getAbsSetOperand(const MachineInstr *MI) {
+static const MachineOperand &getAbsSetOperand(const MachineInstr &MI) {
assert(isLoadAbsSet(MI));
- return MI->getOperand(1);
+ return MI.getOperand(1);
}
@@ -571,8 +571,8 @@ static const MachineOperand &getAbsSetOp
// if there is a new value store in the packet. Corollary: if there is
// already a store in a packet, there can not be a new value store.
// Arch Spec: 3.4.4.2
-bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr *MI,
- const MachineInstr *PacketMI, unsigned DepReg) {
+bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI,
+ const MachineInstr &PacketMI, unsigned DepReg) {
// Make sure we are looking at the store, that can be promoted.
if (!HII->mayBeNewStore(MI))
return false;
@@ -582,7 +582,7 @@ bool HexagonPacketizerList::canPromoteTo
if (Val.isReg() && Val.getReg() != DepReg)
return false;
- const MCInstrDesc& MCID = PacketMI->getDesc();
+ const MCInstrDesc& MCID = PacketMI.getDesc();
// First operand is always the result.
const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
@@ -600,12 +600,12 @@ bool HexagonPacketizerList::canPromoteTo
// Make sure it's NOT the post increment register that we are going to
// new value.
- if (HII->isPostIncrement(MI) &&
+ if (HII->isPostIncrement(&MI) &&
getPostIncrementOperand(MI, HII).getReg() == DepReg) {
return false;
}
- if (HII->isPostIncrement(PacketMI) && PacketMI->mayLoad() &&
+ if (HII->isPostIncrement(&PacketMI) && PacketMI.mayLoad() &&
getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
// If source is post_inc, or absolute-set addressing, it can not feed
// into new value store
@@ -620,8 +620,8 @@ bool HexagonPacketizerList::canPromoteTo
// If the source that feeds the store is predicated, new value store must
// also be predicated.
- if (HII->isPredicated(*PacketMI)) {
- if (!HII->isPredicated(*MI))
+ if (HII->isPredicated(PacketMI)) {
+ if (!HII->isPredicated(MI))
return false;
// Check to make sure that they both will have their predicates
@@ -631,7 +631,7 @@ bool HexagonPacketizerList::canPromoteTo
const TargetRegisterClass* predRegClass = nullptr;
// Get predicate register used in the source instruction.
- for (auto &MO : PacketMI->operands()) {
+ for (auto &MO : PacketMI.operands()) {
if (!MO.isReg())
continue;
predRegNumSrc = MO.getReg();
@@ -643,7 +643,7 @@ bool HexagonPacketizerList::canPromoteTo
"predicate register not found in a predicated PacketMI instruction");
// Get predicate register used in new-value store instruction.
- for (auto &MO : MI->operands()) {
+ for (auto &MO : MI.operands()) {
if (!MO.isReg())
continue;
predRegNumDst = MO.getReg();
@@ -664,7 +664,7 @@ bool HexagonPacketizerList::canPromoteTo
// sense, i.e, either both should be negated or both should be non-negated.
if (predRegNumDst != predRegNumSrc ||
HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
- getPredicateSense(*MI, HII) != getPredicateSense(*PacketMI, HII))
+ getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
return false;
}
@@ -680,19 +680,19 @@ bool HexagonPacketizerList::canPromoteTo
for (auto I : CurrentPacketMIs) {
SUnit *TempSU = MIToSUnit.find(I)->second;
- MachineInstr* TempMI = TempSU->getInstr();
+ MachineInstr &TempMI = *TempSU->getInstr();
// Following condition is true for all the instructions until PacketMI is
// reached (StartCheck is set to 0 before the for loop).
// StartCheck flag is 1 for all the instructions after PacketMI.
- if (TempMI != PacketMI && !StartCheck) // Start processing only after
- continue; // encountering PacketMI.
+ if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
+ continue; // encountering PacketMI.
StartCheck = 1;
- if (TempMI == PacketMI) // We don't want to check PacketMI for dependence.
+ if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
continue;
- for (auto &MO : MI->operands())
+ for (auto &MO : MI.operands())
if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
return false;
}
@@ -703,9 +703,9 @@ bool HexagonPacketizerList::canPromoteTo
// The following store can not be dot new.
// Eg. r0 = add(r0, #3)
// memw(r1+r0<<#2) = r0
- if (!HII->isPostIncrement(MI)) {
- for (unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
- const MachineOperand &MO = MI->getOperand(opNum);
+ if (!HII->isPostIncrement(&MI)) {
+ for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
+ const MachineOperand &MO = MI.getOperand(opNum);
if (MO.isReg() && MO.getReg() == DepReg)
return false;
}
@@ -715,7 +715,7 @@ bool HexagonPacketizerList::canPromoteTo
// do not newify the store. Eg.
// %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
// S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
- for (auto &MO : PacketMI->operands()) {
+ for (auto &MO : PacketMI.operands()) {
if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
continue;
unsigned R = MO.getReg();
@@ -728,7 +728,7 @@ bool HexagonPacketizerList::canPromoteTo
// just-in-case. For example, we cannot newify R2 in the following case:
// %R3<def> = A2_tfrsi 0;
// S2_storeri_io %R0<kill>, 0, %R2<kill>, %D1<imp-use,kill>;
- for (auto &MO : MI->operands()) {
+ for (auto &MO : MI.operands()) {
if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
return false;
}
@@ -738,14 +738,14 @@ bool HexagonPacketizerList::canPromoteTo
}
// Can this MI to promoted to either new value store or new value jump.
-bool HexagonPacketizerList::canPromoteToNewValue(const MachineInstr *MI,
+bool HexagonPacketizerList::canPromoteToNewValue(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg,
MachineBasicBlock::iterator &MII) {
if (!HII->mayBeNewStore(MI))
return false;
// Check to see the store can be new value'ed.
- MachineInstr *PacketMI = PacketSU->getInstr();
+ MachineInstr &PacketMI = *PacketSU->getInstr();
if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
return true;
@@ -754,8 +754,8 @@ bool HexagonPacketizerList::canPromoteTo
return false;
}
-static bool isImplicitDependency(const MachineInstr *I, unsigned DepReg) {
- for (auto &MO : I->operands())
+static bool isImplicitDependency(const MachineInstr &I, unsigned DepReg) {
+ for (auto &MO : I.operands())
if (MO.isReg() && MO.isDef() && (MO.getReg() == DepReg) && MO.isImplicit())
return true;
return false;
@@ -766,7 +766,7 @@ static bool isImplicitDependency(const M
// 1. dot new on predicate - V2/V3/V4
// 2. dot new on stores NV/ST - V4
// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
-bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr *MI,
+bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
// Already a dot new instruction.
@@ -776,15 +776,15 @@ bool HexagonPacketizerList::canPromoteTo
if (!isNewifiable(MI, RC))
return false;
- const MachineInstr *PI = PacketSU->getInstr();
+ const MachineInstr &PI = *PacketSU->getInstr();
// The "new value" cannot come from inline asm.
- if (PI->isInlineAsm())
+ if (PI.isInlineAsm())
return false;
// IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
// sense.
- if (PI->isImplicitDef())
+ if (PI.isImplicitDef())
return false;
// If dependency is trough an implicitly defined register, we should not
@@ -792,7 +792,7 @@ bool HexagonPacketizerList::canPromoteTo
if (isImplicitDependency(PI, DepReg))
return false;
- const MCInstrDesc& MCID = PI->getDesc();
+ const MCInstrDesc& MCID = PI.getDesc();
const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass)
return false;
@@ -801,7 +801,7 @@ bool HexagonPacketizerList::canPromoteTo
// bug 5670: until that is fixed
// TODO: MI->isIndirectBranch() and IsRegisterJump(MI)
if (RC == &Hexagon::PredRegsRegClass)
- if (HII->isCondInst(MI) || MI->isReturn())
+ if (HII->isCondInst(MI) || MI.isReturn())
return HII->predCanBeUsedAsDotNew(PI, DepReg);
if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
@@ -837,9 +837,9 @@ bool HexagonPacketizerList::canPromoteTo
// The P3 from a) and d) will be complements after
// a)'s P3 is converted to .new form
// Anti-dep between c) and b) is irrelevant for this case
-bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr* MI,
+bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr &MI,
unsigned DepReg) {
- SUnit *PacketSUDep = MIToSUnit.find(MI)->second;
+ SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
for (auto I : CurrentPacketMIs) {
// We only care for dependencies to predicated instructions
@@ -931,7 +931,7 @@ bool HexagonPacketizerList::arePredicate
// above example. Now I need to see if there is an anti dependency
// from c) to any other instruction in the same packet on the pred
// reg of interest.
- if (restrictingDepExistInPacket(I, Dep.getReg()))
+ if (restrictingDepExistInPacket(*I, Dep.getReg()))
return false;
}
}
@@ -948,7 +948,7 @@ bool HexagonPacketizerList::arePredicate
Hexagon::PredRegsRegClass.contains(PReg1) &&
Hexagon::PredRegsRegClass.contains(PReg2) &&
getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
- HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2);
+ HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
}
// Initialize packetizer flags.
@@ -999,10 +999,10 @@ bool HexagonPacketizerList::isSoloInstru
// From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
// trap, pause, barrier, icinva, isync, and syncht are solo instructions.
// They must not be grouped with other instructions in a packet.
- if (isSchedBarrier(&MI))
+ if (isSchedBarrier(MI))
return true;
- if (HII->isSolo(&MI))
+ if (HII->isSolo(MI))
return true;
if (MI.getOpcode() == Hexagon::A2_nop)
@@ -1019,9 +1019,9 @@ bool HexagonPacketizerList::isSoloInstru
// cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
// Doing the test only one way saves the amount of code in this function,
// since every test would need to be repeated with the MI and MJ reversed.
-static bool cannotCoexistAsymm(const MachineInstr *MI, const MachineInstr *MJ,
+static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
const HexagonInstrInfo &HII) {
- const MachineFunction *MF = MI->getParent()->getParent();
+ const MachineFunction *MF = MI.getParent()->getParent();
if (MF->getSubtarget<HexagonSubtarget>().hasV60TOpsOnly() &&
HII.isHVXMemWithAIndirect(MI, MJ))
return true;
@@ -1030,9 +1030,9 @@ static bool cannotCoexistAsymm(const Mac
// able to remove the asm out after packetizing (i.e. if the asm must be
// moved past the bundle). Similarly, two asms cannot be together to avoid
// complications when determining their relative order outside of a bundle.
- if (MI->isInlineAsm())
- return MJ->isInlineAsm() || MJ->isBranch() || MJ->isBarrier() ||
- MJ->isCall() || MJ->isTerminator();
+ if (MI.isInlineAsm())
+ return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
+ MJ.isCall() || MJ.isTerminator();
// "False" really means that the quick check failed to determine if
// I and J cannot coexist.
@@ -1041,8 +1041,8 @@ static bool cannotCoexistAsymm(const Mac
// Full, symmetric check.
-bool HexagonPacketizerList::cannotCoexist(const MachineInstr *MI,
- const MachineInstr *MJ) {
+bool HexagonPacketizerList::cannotCoexist(const MachineInstr &MI,
+ const MachineInstr &MJ) {
return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
}
@@ -1052,10 +1052,10 @@ void HexagonPacketizerList::unpacketizeS
MachineBasicBlock::instr_iterator NextI;
for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
NextI = std::next(I);
- MachineInstr *MI = &*I;
- if (MI->isBundle())
+ MachineInstr &MI = *I;
+ if (MI.isBundle())
BundleIt = I;
- if (!MI->isInsideBundle())
+ if (!MI.isInsideBundle())
continue;
// Decide on where to insert the instruction that we are pulling out.
@@ -1065,9 +1065,9 @@ void HexagonPacketizerList::unpacketizeS
// other instructions in the bundle read, then we need to place it
// after the bundle (to preserve the bundle semantics).
bool InsertBeforeBundle;
- if (MI->isInlineAsm())
- InsertBeforeBundle = !hasWriteToReadDep(*MI, *BundleIt, HRI);
- else if (MI->isDebugValue())
+ if (MI.isInlineAsm())
+ InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
+ else if (MI.isDebugValue())
InsertBeforeBundle = true;
else
continue;
@@ -1078,8 +1078,8 @@ void HexagonPacketizerList::unpacketizeS
}
// Check if a given instruction is of class "system".
-static bool isSystemInstr(const MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+static bool isSystemInstr(const MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::Y2_barrier:
case Hexagon::Y2_dcfetchbo:
@@ -1088,24 +1088,24 @@ static bool isSystemInstr(const MachineI
return false;
}
-bool HexagonPacketizerList::hasDeadDependence(const MachineInstr *I,
- const MachineInstr *J) {
+bool HexagonPacketizerList::hasDeadDependence(const MachineInstr &I,
+ const MachineInstr &J) {
// The dependence graph may not include edges between dead definitions,
// so without extra checks, we could end up packetizing two instruction
// defining the same (dead) register.
- if (I->isCall() || J->isCall())
+ if (I.isCall() || J.isCall())
return false;
- if (HII->isPredicated(*I) || HII->isPredicated(*J))
+ if (HII->isPredicated(I) || HII->isPredicated(J))
return false;
BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
- for (auto &MO : I->operands()) {
+ for (auto &MO : I.operands()) {
if (!MO.isReg() || !MO.isDef() || !MO.isDead())
continue;
DeadDefs[MO.getReg()] = true;
}
- for (auto &MO : J->operands()) {
+ for (auto &MO : J.operands()) {
if (!MO.isReg() || !MO.isDef() || !MO.isDead())
continue;
unsigned R = MO.getReg();
@@ -1115,8 +1115,8 @@ bool HexagonPacketizerList::hasDeadDepen
return false;
}
-bool HexagonPacketizerList::hasControlDependence(const MachineInstr *I,
- const MachineInstr *J) {
+bool HexagonPacketizerList::hasControlDependence(const MachineInstr &I,
+ const MachineInstr &J) {
// A save callee-save register function call can only be in a packet
// with instructions that don't write to the callee-save registers.
if ((HII->isSaveCalleeSavedRegsCall(I) &&
@@ -1132,10 +1132,10 @@ bool HexagonPacketizerList::hasControlDe
// \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
// contain a speculative indirect jump,
// a new-value compare jump or a dealloc_return.
- auto isBadForLoopN = [this] (const MachineInstr *MI) -> bool {
- if (MI->isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
+ auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
+ if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
return true;
- if (HII->isPredicated(*MI) && HII->isPredicatedNew(*MI) && HII->isJumpR(MI))
+ if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
return true;
return false;
};
@@ -1148,13 +1148,13 @@ bool HexagonPacketizerList::hasControlDe
// dealloc_return cannot appear in the same packet as a conditional or
// unconditional jump.
return HII->isDeallocRet(I) &&
- (J->isBranch() || J->isCall() || J->isBarrier());
+ (J.isBranch() || J.isCall() || J.isBarrier());
}
-bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr *I,
- const MachineInstr *J) {
+bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr &I,
+ const MachineInstr &J) {
bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
- bool StoreI = I->mayStore(), StoreJ = J->mayStore();
+ bool StoreI = I.mayStore(), StoreJ = J.mayStore();
if ((SysI && StoreJ) || (SysJ && StoreI))
return true;
@@ -1177,18 +1177,18 @@ bool HexagonPacketizerList::hasV4Specifi
// SUJ is the current instruction inside the current packet against which that
// SUI will be packetized.
bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
- MachineInstr *I = SUI->getInstr();
- MachineInstr *J = SUJ->getInstr();
- assert(I && J && "Unable to packetize null instruction!");
+ assert(SUI->getInstr() && SUJ->getInstr());
+ MachineInstr &I = *SUI->getInstr();
+ MachineInstr &J = *SUJ->getInstr();
// Clear IgnoreDepMIs when Packet starts.
if (CurrentPacketMIs.size() == 1)
IgnoreDepMIs.clear();
- MachineBasicBlock::iterator II = I;
+ MachineBasicBlock::iterator II = I.getIterator();
// Solo instructions cannot go in the packet.
- assert(!isSoloInstruction(*I) && "Unexpected solo instr!");
+ assert(!isSoloInstruction(I) && "Unexpected solo instr!");
if (cannotCoexist(I, J))
return false;
@@ -1205,23 +1205,23 @@ bool HexagonPacketizerList::isLegalToPac
return false;
// If an instruction feeds new value jump, glue it.
- MachineBasicBlock::iterator NextMII = I;
+ MachineBasicBlock::iterator NextMII = I.getIterator();
++NextMII;
- if (NextMII != I->getParent()->end() && HII->isNewValueJump(&*NextMII)) {
+ if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
MachineInstr &NextMI = *NextMII;
bool secondRegMatch = false;
const MachineOperand &NOp0 = NextMI.getOperand(0);
const MachineOperand &NOp1 = NextMI.getOperand(1);
- if (NOp1.isReg() && I->getOperand(0).getReg() == NOp1.getReg())
+ if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
secondRegMatch = true;
- for (auto I : CurrentPacketMIs) {
- SUnit *PacketSU = MIToSUnit.find(I)->second;
- MachineInstr *PI = PacketSU->getInstr();
+ for (auto T : CurrentPacketMIs) {
+ SUnit *PacketSU = MIToSUnit.find(T)->second;
+ MachineInstr &PI = *PacketSU->getInstr();
// NVJ can not be part of the dual jump - Arch Spec: section 7.8.
- if (PI->isCall()) {
+ if (PI.isCall()) {
Dependence = true;
break;
}
@@ -1233,14 +1233,14 @@ bool HexagonPacketizerList::isLegalToPac
// 3. If the second operand of the nvj is newified, (which means
// first operand is also a reg), first reg is not defined in
// the same packet.
- if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
+ if (PI.getOpcode() == Hexagon::S2_allocframe || PI.mayStore() ||
HII->isLoopN(PI)) {
Dependence = true;
break;
}
// Check #2/#3.
const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
- if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
+ if (OpR.isReg() && PI.modifiesRegister(OpR.getReg(), HRI)) {
Dependence = true;
break;
}
@@ -1291,7 +1291,7 @@ bool HexagonPacketizerList::isLegalToPac
RC = HRI->getMinimalPhysRegClass(DepReg);
}
- if (I->isCall() || I->isReturn() || HII->isTailCall(I)) {
+ if (I.isCall() || I.isReturn() || HII->isTailCall(I)) {
if (!isRegDependence(DepType))
continue;
if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
@@ -1324,8 +1324,8 @@ bool HexagonPacketizerList::isLegalToPac
// For predicated instructions, if the predicates are complements then
// there can be no dependence.
- if (HII->isPredicated(*I) && HII->isPredicated(*J) &&
- arePredicatesComplements(*I, *J)) {
+ if (HII->isPredicated(I) && HII->isPredicated(J) &&
+ arePredicatesComplements(I, J)) {
// Not always safe to do this translation.
// DAG Builder attempts to reduce dependence edges using transitive
// nature of dependencies. Here is an example:
@@ -1338,24 +1338,24 @@ bool HexagonPacketizerList::isLegalToPac
// However, there is no dependence edge between (1)->(3). This results
// in all 3 instructions going in the same packet. We ignore dependce
// only once to avoid this situation.
- auto Itr = std::find(IgnoreDepMIs.begin(), IgnoreDepMIs.end(), J);
+ auto Itr = std::find(IgnoreDepMIs.begin(), IgnoreDepMIs.end(), &J);
if (Itr != IgnoreDepMIs.end()) {
Dependence = true;
return false;
}
- IgnoreDepMIs.push_back(I);
+ IgnoreDepMIs.push_back(&I);
continue;
}
// Ignore Order dependences between unconditional direct branches
// and non-control-flow instructions.
- if (isDirectJump(I) && !J->isBranch() && !J->isCall() &&
+ if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
DepType == SDep::Order)
continue;
// Ignore all dependences for jumps except for true and output
// dependences.
- if (I->isConditionalBranch() && DepType != SDep::Data &&
+ if (I.isConditionalBranch() && DepType != SDep::Data &&
DepType != SDep::Output)
continue;
@@ -1377,7 +1377,7 @@ bool HexagonPacketizerList::isLegalToPac
unsigned DepReg = SUJ->Succs[i].getReg();
// Check if I and J really defines DepReg.
- if (!I->definesRegister(DepReg) && !J->definesRegister(DepReg))
+ if (!I.definesRegister(DepReg) && !J.definesRegister(DepReg))
continue;
FoundSequentialDependence = true;
break;
@@ -1391,15 +1391,15 @@ bool HexagonPacketizerList::isLegalToPac
// 4. Load followed by any memory operation is allowed.
if (DepType == SDep::Order) {
if (!PacketizeVolatiles) {
- bool OrdRefs = I->hasOrderedMemoryRef() || J->hasOrderedMemoryRef();
+ bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
if (OrdRefs) {
FoundSequentialDependence = true;
break;
}
}
// J is first, I is second.
- bool LoadJ = J->mayLoad(), StoreJ = J->mayStore();
- bool LoadI = I->mayLoad(), StoreI = I->mayStore();
+ bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
+ bool LoadI = I.mayLoad(), StoreI = I.mayStore();
if (StoreJ) {
// Two stores are only allowed on V4+. Load following store is never
// allowed.
@@ -1424,14 +1424,14 @@ bool HexagonPacketizerList::isLegalToPac
// between ALLOCFRAME and subsequent store, allow it to be packetized
// in a same packet. This implies that the store is using the caller's
// SP. Hence, offset needs to be updated accordingly.
- if (DepType == SDep::Data && J->getOpcode() == Hexagon::S2_allocframe) {
- unsigned Opc = I->getOpcode();
+ if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
+ unsigned Opc = I.getOpcode();
switch (Opc) {
case Hexagon::S2_storerd_io:
case Hexagon::S2_storeri_io:
case Hexagon::S2_storerh_io:
case Hexagon::S2_storerb_io:
- if (I->getOperand(0).getReg() == HRI->getStackRegister()) {
+ if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
// Since this store is to be glued with allocframe in the same
// packet, it will use SP of the previous stack frame, i.e.
// caller's SP. Therefore, we need to recalculate offset
@@ -1451,12 +1451,12 @@ bool HexagonPacketizerList::isLegalToPac
// R0 = ... ; SUI
// Those cannot be packetized together, since the call will observe
// the effect of the assignment to R0.
- if (DepType == SDep::Anti && J->isCall()) {
+ if (DepType == SDep::Anti && J.isCall()) {
// Check if I defines any volatile register. We should also check
// registers that the call may read, but these happen to be a
// subset of the volatile register set.
- for (const MCPhysReg *P = J->getDesc().ImplicitDefs; P && *P; ++P) {
- if (!I->modifiesRegister(*P, HRI))
+ for (const MCPhysReg *P = J.getDesc().ImplicitDefs; P && *P; ++P) {
+ if (!I.modifiesRegister(*P, HRI))
continue;
FoundSequentialDependence = true;
break;
@@ -1484,9 +1484,9 @@ bool HexagonPacketizerList::isLegalToPac
}
bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
- MachineInstr *I = SUI->getInstr();
- MachineInstr *J = SUJ->getInstr();
- assert(I && J && "Unable to packetize null instruction!");
+ assert(SUI->getInstr() && SUJ->getInstr());
+ MachineInstr &I = *SUI->getInstr();
+ MachineInstr &J = *SUJ->getInstr();
if (cannotCoexist(I, J))
return false;
@@ -1512,7 +1512,7 @@ bool HexagonPacketizerList::isLegalToPru
MachineBasicBlock::iterator
HexagonPacketizerList::addToPacket(MachineInstr &MI) {
- MachineBasicBlock::iterator MII = MI;
+ MachineBasicBlock::iterator MII = MI.getIterator();
MachineBasicBlock *MBB = MI.getParent();
if (MI.isImplicitDef()) {
unsigned R = MI.getOperand(0).getReg();
@@ -1524,7 +1524,7 @@ HexagonPacketizerList::addToPacket(Machi
}
assert(ResourceTracker->canReserveResources(MI));
- bool ExtMI = HII->isExtended(&MI) || HII->isConstExtended(&MI);
+ bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
bool Good = true;
if (GlueToNewValueJump) {
@@ -1537,7 +1537,7 @@ HexagonPacketizerList::addToPacket(Machi
if (ExtMI)
Good = tryAllocateResourcesForConstExt(true);
- bool ExtNvjMI = HII->isExtended(&NvjMI) || HII->isConstExtended(&NvjMI);
+ bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
if (Good) {
if (ResourceTracker->canReserveResources(NvjMI))
ResourceTracker->reserveResources(NvjMI);
@@ -1571,9 +1571,9 @@ HexagonPacketizerList::addToPacket(Machi
if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
endPacket(MBB, MI);
if (PromotedToDotNew)
- demoteToDotOld(&MI);
+ demoteToDotOld(MI);
if (GlueAllocframeStore) {
- useCalleesSP(&MI);
+ useCalleesSP(MI);
GlueAllocframeStore = false;
}
ResourceTracker->reserveResources(MI);
@@ -1591,18 +1591,18 @@ void HexagonPacketizerList::endPacket(Ma
}
bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) {
- return !producesStall(&MI);
+ return !producesStall(MI);
}
// Return true when ConsMI uses a register defined by ProdMI.
-static bool isDependent(const MachineInstr *ProdMI,
- const MachineInstr *ConsMI) {
- if (!ProdMI->getOperand(0).isReg())
+static bool isDependent(const MachineInstr &ProdMI,
+ const MachineInstr &ConsMI) {
+ if (!ProdMI.getOperand(0).isReg())
return false;
- unsigned DstReg = ProdMI->getOperand(0).getReg();
+ unsigned DstReg = ProdMI.getOperand(0).getReg();
- for (auto &Op : ConsMI->operands())
+ for (auto &Op : ConsMI.operands())
if (Op.isReg() && Op.isUse() && Op.getReg() == DstReg)
// The MIs depend on each other.
return true;
@@ -1611,7 +1611,7 @@ static bool isDependent(const MachineIns
}
// V60 forward scheduling.
-bool HexagonPacketizerList::producesStall(const MachineInstr *I) {
+bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
// Check whether the previous packet is in a different loop. If this is the
// case, there is little point in trying to avoid a stall because that would
// favor the rare case (loop entry) over the common case (loop iteration).
@@ -1621,7 +1621,7 @@ bool HexagonPacketizerList::producesStal
// backedge.
if (!OldPacketMIs.empty()) {
auto *OldBB = OldPacketMIs.front()->getParent();
- auto *ThisBB = I->getParent();
+ auto *ThisBB = I.getParent();
if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
return false;
}
@@ -1629,9 +1629,9 @@ bool HexagonPacketizerList::producesStal
// Check for stall between two vector instructions.
if (HII->isV60VectorInstruction(I)) {
for (auto J : OldPacketMIs) {
- if (!HII->isV60VectorInstruction(J))
+ if (!HII->isV60VectorInstruction(*J))
continue;
- if (isDependent(J, I) && !HII->isVecUsableNextPacket(J, I))
+ if (isDependent(*J, I) && !HII->isVecUsableNextPacket(*J, I))
return true;
}
return false;
@@ -1641,17 +1641,17 @@ bool HexagonPacketizerList::producesStal
// there is no definition of a use in the current packet, because it
// may be a candidate for .new.
for (auto J : CurrentPacketMIs)
- if (!HII->isV60VectorInstruction(J) && isDependent(J, I))
+ if (!HII->isV60VectorInstruction(*J) && isDependent(*J, I))
return false;
// Check for stall between I and instructions in the previous packet.
if (MF.getSubtarget<HexagonSubtarget>().useBSBScheduling()) {
for (auto J : OldPacketMIs) {
- if (HII->isV60VectorInstruction(J))
+ if (HII->isV60VectorInstruction(*J))
continue;
- if (!HII->isLateInstrFeedsEarlyInstr(J, I))
+ if (!HII->isLateInstrFeedsEarlyInstr(*J, I))
continue;
- if (isDependent(J, I) && !HII->canExecuteInBundle(J, I))
+ if (isDependent(*J, I) && !HII->canExecuteInBundle(*J, I))
return true;
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h?rev=277220&r1=277219&r2=277220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.h Fri Jul 29 16:49:42 2016
@@ -73,44 +73,44 @@ public:
void unpacketizeSoloInstrs(MachineFunction &MF);
protected:
- bool isCallDependent(const MachineInstr* MI, SDep::Kind DepType,
+ bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
unsigned DepReg);
- bool promoteToDotCur(MachineInstr* MI, SDep::Kind DepType,
+ bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
MachineBasicBlock::iterator &MII,
- const TargetRegisterClass* RC);
- bool canPromoteToDotCur(const MachineInstr* MI, const SUnit* PacketSU,
+ const TargetRegisterClass *RC);
+ bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
unsigned DepReg, MachineBasicBlock::iterator &MII,
- const TargetRegisterClass* RC);
+ const TargetRegisterClass *RC);
void cleanUpDotCur();
- bool promoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
+ bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
MachineBasicBlock::iterator &MII,
- const TargetRegisterClass* RC);
- bool canPromoteToDotNew(const MachineInstr* MI, const SUnit* PacketSU,
+ const TargetRegisterClass *RC);
+ bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
unsigned DepReg, MachineBasicBlock::iterator &MII,
- const TargetRegisterClass* RC);
- bool canPromoteToNewValue(const MachineInstr* MI, const SUnit* PacketSU,
+ const TargetRegisterClass *RC);
+ bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
unsigned DepReg, MachineBasicBlock::iterator &MII);
- bool canPromoteToNewValueStore(const MachineInstr* MI,
- const MachineInstr* PacketMI, unsigned DepReg);
- bool demoteToDotOld(MachineInstr* MI);
- bool useCallersSP(MachineInstr *MI);
- void useCalleesSP(MachineInstr *MI);
+ bool canPromoteToNewValueStore(const MachineInstr &MI,
+ const MachineInstr &PacketMI, unsigned DepReg);
+ bool demoteToDotOld(MachineInstr &MI);
+ bool useCallersSP(MachineInstr &MI);
+ void useCalleesSP(MachineInstr &MI);
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
- bool restrictingDepExistInPacket(MachineInstr*, unsigned);
- bool isNewifiable(const MachineInstr *MI, const TargetRegisterClass *NewRC);
- bool isCurifiable(MachineInstr* MI);
- bool cannotCoexist(const MachineInstr *MI, const MachineInstr *MJ);
+ bool restrictingDepExistInPacket(MachineInstr&, unsigned);
+ bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
+ bool isCurifiable(MachineInstr &MI);
+ bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
inline bool isPromotedToDotNew() const {
return PromotedToDotNew;
}
bool tryAllocateResourcesForConstExt(bool Reserve);
bool canReserveResourcesForConstExt();
void reserveResourcesForConstExt();
- bool hasDeadDependence(const MachineInstr *I, const MachineInstr *J);
- bool hasControlDependence(const MachineInstr *I, const MachineInstr *J);
- bool hasV4SpecificDependence(const MachineInstr *I, const MachineInstr *J);
- bool producesStall(const MachineInstr *MI);
+ bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
+ bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
+ bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J);
+ bool producesStall(const MachineInstr &MI);
};
} // namespace llvm
#endif // HEXAGONVLIWPACKETIZER_H
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