[llvm] r277184 - GlobalISel: add generic conditional branch.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 10:58:00 PDT 2016
Author: tnorthover
Date: Fri Jul 29 12:58:00 2016
New Revision: 277184
URL: http://llvm.org/viewvc/llvm-project?rev=277184&view=rev
Log:
GlobalISel: add generic conditional branch.
Just the basic equivalent to DAG's condbr for now, we'll get to things like
br_cc when we start doing more legalization.
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/trunk/include/llvm/Target/GenericOpcodes.td
llvm/trunk/include/llvm/Target/TargetOpcodes.def
llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=277184&r1=277183&r2=277184&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Fri Jul 29 12:58:00 2016
@@ -140,6 +140,17 @@ public:
/// \return a MachineInstrBuilder for the newly created instruction.
MachineInstrBuilder buildBr(MachineBasicBlock &BB);
+ /// Build and insert G_BRCOND \p Ty \p Tst, \p Dest
+ ///
+ /// G_BRCOND is a conditional branch to \p Dest. At the beginning of
+ /// legalization, \p Ty will be a single bit (s1). Targets with interesting
+ /// flags registers may change this.
+ ///
+ /// \pre setBasicBlock or setMI must have been called.
+ ///
+ /// \return The newly created instruction.
+ MachineInstrBuilder buildBrCond(LLT Ty, unsigned Tst, MachineBasicBlock &BB);
+
/// Build and insert \p Res<def> = COPY Op
///
/// Register-to-register COPY sets \p Res to \p Op.
Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=277184&r1=277183&r2=277184&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Fri Jul 29 12:58:00 2016
@@ -135,6 +135,16 @@ def G_BR : Instruction {
let hasSideEffects = 0;
let isBranch = 1;
let isTerminator = 1;
+ let isBarrier = 1;
+}
+
+// Generic conditional branch.
+def G_BRCOND : Instruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins unknown:$tst, unknown:$truebb);
+ let hasSideEffects = 0;
+ let isBranch = 1;
+ let isTerminator = 1;
}
// TODO: Add the other generic opcodes.
Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=277184&r1=277183&r2=277184&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Fri Jul 29 12:58:00 2016
@@ -199,6 +199,9 @@ HANDLE_TARGET_OPCODE(G_LOAD)
/// Generic store.
HANDLE_TARGET_OPCODE(G_STORE)
+/// Generic conditional branch instruction.
+HANDLE_TARGET_OPCODE(G_BRCOND)
+
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)
Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=277184&r1=277183&r2=277184&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Fri Jul 29 12:58:00 2016
@@ -104,13 +104,20 @@ bool IRTranslator::translateReturn(const
bool IRTranslator::translateBr(const Instruction &Inst) {
assert(isa<BranchInst>(Inst) && "Branch expected");
const BranchInst &BrInst = *cast<BranchInst>(&Inst);
- if (BrInst.isUnconditional()) {
- const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getOperand(0));
- MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
- MIRBuilder.buildBr(TgtBB);
- } else {
- assert(0 && "Not yet implemented");
+
+ unsigned Succ = 0;
+ if (!BrInst.isUnconditional()) {
+ // We want a G_BRCOND to the true BB followed by an unconditional branch.
+ unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
+ const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
+ MachineBasicBlock &TrueBB = getOrCreateBB(TrueTgt);
+ MIRBuilder.buildBrCond(LLT{*BrInst.getCondition()->getType()}, Tst, TrueBB);
}
+
+ const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
+ MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
+ MIRBuilder.buildBr(TgtBB);
+
// Link successors.
MachineBasicBlock &CurBB = MIRBuilder.getMBB();
for (const BasicBlock *Succ : BrInst.successors())
Modified: llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp?rev=277184&r1=277183&r2=277184&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp Fri Jul 29 12:58:00 2016
@@ -95,7 +95,13 @@ MachineInstrBuilder MachineIRBuilder::bu
return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
}
-MachineInstrBuilder MachineIRBuilder::buildLoad(LLT VTy, LLT PTy, unsigned Res,
+MachineInstrBuilder MachineIRBuilder::buildBrCond(LLT Ty, unsigned Tst,
+ MachineBasicBlock &Dest) {
+ return buildInstr(TargetOpcode::G_BRCOND, Ty).addUse(Tst).addMBB(&Dest);
+}
+
+
+ MachineInstrBuilder MachineIRBuilder::buildLoad(LLT VTy, LLT PTy, unsigned Res,
unsigned Addr,
MachineMemOperand &MMO) {
return buildInstr(TargetOpcode::G_LOAD, {VTy, PTy})
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=277184&r1=277183&r2=277184&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Fri Jul 29 12:58:00 2016
@@ -58,6 +58,37 @@ end:
ret void
}
+; Tests for conditional br.
+; CHECK-LABEL: name: condbr
+; CHECK: body:
+;
+; Entry basic block.
+; CHECK: {{[0-9a-zA-Z._-]+}}:
+;
+; Make sure we have two successors
+; CHECK-NEXT: successors: %[[TRUE:[0-9a-zA-Z._-]+]]({{0x[a-f0-9]+ / 0x[a-f0-9]+}} = 50.00%),
+; CHECK: %[[FALSE:[0-9a-zA-Z._-]+]]({{0x[a-f0-9]+ / 0x[a-f0-9]+}} = 50.00%)
+;
+; Check that we emit the correct branch.
+; CHECK: [[ADDR:%.*]](64) = COPY %x0
+; CHECK: [[TST:%.*]](1) = G_LOAD { s1, p0 } [[ADDR]]
+; CHECK: G_BRCOND s1 [[TST]], %[[TRUE]]
+; CHECK: G_BR unsized %[[FALSE]]
+;
+; Check that each successor contains the return instruction.
+; CHECK: [[TRUE]]:
+; CHECK-NEXT: RET_ReallyLR
+; CHECK: [[FALSE]]:
+; CHECK-NEXT: RET_ReallyLR
+define void @condbr(i1* %tstaddr) {
+ %tst = load i1, i1* %tstaddr
+ br i1 %tst, label %true, label %false
+true:
+ ret void
+false:
+ ret void
+}
+
; Tests for or.
; CHECK-LABEL: name: ori64
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
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