[llvm] r277172 - [GlobalISel] Add G_XOR.

[Ahmed Bougacha via llvm-commits]

Author: ab
Date: Fri Jul 29 11:56:20 2016
New Revision: 277172

URL: http://llvm.org/viewvc/llvm-project?rev=277172&view=rev
Log:
[GlobalISel] Add G_XOR.

Modified:
    llvm/trunk/include/llvm/Target/GenericOpcodes.td
    llvm/trunk/include/llvm/Target/TargetOpcodes.def
    llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=277172&r1=277171&r2=277172&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
+++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Fri Jul 29 11:56:20 2016
@@ -76,6 +76,14 @@ def G_OR : Instruction {
   let isCommutable = 1;
 }
 
+// Generic bitwise xor.
+def G_XOR : Instruction {
+  let OutOperandList = (outs unknown:$dst);
+  let InOperandList = (ins unknown:$src1, unknown:$src2);
+  let hasSideEffects = 0;
+  let isCommutable = 1;
+}
+
 //------------------------------------------------------------------------------
 // Memory ops
 //------------------------------------------------------------------------------

Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.def?rev=277172&r1=277171&r2=277172&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.def (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.def Fri Jul 29 11:56:20 2016
@@ -168,6 +168,9 @@ HANDLE_TARGET_OPCODE(G_AND)
 /// Generic Bitwise-OR instruction.
 HANDLE_TARGET_OPCODE(G_OR)
 
+/// Generic Bitwise-OR instruction.
+HANDLE_TARGET_OPCODE(G_XOR)
+
 /// Generic instruction to materialize the address of an alloca or other
 /// stack-based object.
 HANDLE_TARGET_OPCODE(G_FRAME_INDEX)

Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=277172&r1=277171&r2=277172&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Fri Jul 29 11:56:20 2016
@@ -199,6 +199,8 @@ bool IRTranslator::translate(const Instr
     return translateBinaryOp(TargetOpcode::G_AND, Inst);
   case Instruction::Or:
     return translateBinaryOp(TargetOpcode::G_OR, Inst);
+  case Instruction::Xor:
+    return translateBinaryOp(TargetOpcode::G_XOR, Inst);
 
   // Branch operations.
   case Instruction::Br:

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=277172&r1=277171&r2=277172&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll Fri Jul 29 11:56:20 2016
@@ -81,6 +81,29 @@ define i32 @ori32(i32 %arg1, i32 %arg2)
   ret i32 %res
 }
 
+; Tests for xor.
+; CHECK-LABEL: name: xori64
+; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_XOR s64 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %x0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %x0
+define i64 @xori64(i64 %arg1, i64 %arg2) {
+  %res = xor i64 %arg1, %arg2
+  ret i64 %res
+}
+
+; CHECK-LABEL: name: xori32
+; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_XOR s32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: %w0 = COPY [[RES]]
+; CHECK-NEXT: RET_ReallyLR implicit %w0
+define i32 @xori32(i32 %arg1, i32 %arg2) {
+  %res = xor i32 %arg1, %arg2
+  ret i32 %res
+}
+
 ; Tests for and.
 ; CHECK-LABEL: name: andi64
 ; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0