[llvm] r277166 - Initial support for vectorization using svml (short vector math library).
Matt Masten via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 29 09:42:44 PDT 2016
Author: mmasten
Date: Fri Jul 29 11:42:44 2016
New Revision: 277166
URL: http://llvm.org/viewvc/llvm-project?rev=277166&view=rev
Log:
Initial support for vectorization using svml (short vector math library).
Differential Revision: https://reviews.llvm.org/D19544
Added:
llvm/trunk/test/Transforms/LoopVectorize/X86/svml-calls.ll
Modified:
llvm/trunk/include/llvm/Analysis/TargetLibraryInfo.h
llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp
Modified: llvm/trunk/include/llvm/Analysis/TargetLibraryInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/TargetLibraryInfo.h?rev=277166&r1=277165&r2=277166&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/TargetLibraryInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/TargetLibraryInfo.h Fri Jul 29 11:42:44 2016
@@ -85,8 +85,9 @@ public:
/// addVectorizableFunctionsFromVecLib for filling up the tables of
/// vectorizable functions.
enum VectorLibrary {
- NoLibrary, // Don't use any vector library.
- Accelerate // Use Accelerate framework.
+ NoLibrary, // Don't use any vector library.
+ Accelerate, // Use Accelerate framework.
+ SVML // Intel short vector math library.
};
TargetLibraryInfoImpl();
Modified: llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp?rev=277166&r1=277165&r2=277166&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp Fri Jul 29 11:42:44 2016
@@ -23,9 +23,10 @@ static cl::opt<TargetLibraryInfoImpl::Ve
"No vector functions library"),
clEnumValN(TargetLibraryInfoImpl::Accelerate, "Accelerate",
"Accelerate framework"),
+ clEnumValN(TargetLibraryInfoImpl::SVML, "SVML",
+ "Intel SVML library"),
clEnumValEnd));
-
const char *const TargetLibraryInfoImpl::StandardNames[LibFunc::NumLibFuncs] = {
#define TLI_DEFINE_STRING
#include "llvm/Analysis/TargetLibraryInfo.def"
@@ -1074,6 +1075,75 @@ void TargetLibraryInfoImpl::addVectoriza
};
addVectorizableFunctions(VecFuncs);
break;
+ }
+ case SVML: {
+ const VecDesc VecFuncs[] = {
+ {"sin", "__svml_sin2", 2},
+ {"sin", "__svml_sin4", 4},
+ {"sin", "__svml_sin8", 8},
+
+ {"sinf", "__svml_sinf4", 4},
+ {"sinf", "__svml_sinf8", 8},
+ {"sinf", "__svml_sinf16", 16},
+
+ {"cos", "__svml_cos2", 2},
+ {"cos", "__svml_cos4", 4},
+ {"cos", "__svml_cos8", 8},
+
+ {"cosf", "__svml_cosf4", 4},
+ {"cosf", "__svml_cosf8", 8},
+ {"cosf", "__svml_cosf16", 16},
+
+ {"pow", "__svml_pow2", 2},
+ {"pow", "__svml_pow4", 4},
+ {"pow", "__svml_pow8", 8},
+
+ {"powf", "__svml_powf4", 4},
+ {"powf", "__svml_powf8", 8},
+ {"powf", "__svml_powf16", 16},
+
+ {"llvm.pow.f64", "__svml_pow2", 2},
+ {"llvm.pow.f64", "__svml_pow4", 4},
+ {"llvm.pow.f64", "__svml_pow8", 8},
+
+ {"llvm.pow.f32", "__svml_powf4", 4},
+ {"llvm.pow.f32", "__svml_powf8", 8},
+ {"llvm.pow.f32", "__svml_powf16", 16},
+
+ {"exp", "__svml_exp2", 2},
+ {"exp", "__svml_exp4", 4},
+ {"exp", "__svml_exp8", 8},
+
+ {"expf", "__svml_expf4", 4},
+ {"expf", "__svml_expf8", 8},
+ {"expf", "__svml_expf16", 16},
+
+ {"llvm.exp.f64", "__svml_exp2", 2},
+ {"llvm.exp.f64", "__svml_exp4", 4},
+ {"llvm.exp.f64", "__svml_exp8", 8},
+
+ {"llvm.exp.f32", "__svml_expf4", 4},
+ {"llvm.exp.f32", "__svml_expf8", 8},
+ {"llvm.exp.f32", "__svml_expf16", 16},
+
+ {"log", "__svml_log2", 2},
+ {"log", "__svml_log4", 4},
+ {"log", "__svml_log8", 8},
+
+ {"logf", "__svml_logf4", 4},
+ {"logf", "__svml_logf8", 8},
+ {"logf", "__svml_logf16", 16},
+
+ {"llvm.log.f64", "__svml_log2", 2},
+ {"llvm.log.f64", "__svml_log4", 4},
+ {"llvm.log.f64", "__svml_log8", 8},
+
+ {"llvm.log.f32", "__svml_logf4", 4},
+ {"llvm.log.f32", "__svml_logf8", 8},
+ {"llvm.log.f32", "__svml_logf16", 16},
+ };
+ addVectorizableFunctions(VecFuncs);
+ break;
}
case NoLibrary:
break;
Added: llvm/trunk/test/Transforms/LoopVectorize/X86/svml-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/svml-calls.ll?rev=277166&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/X86/svml-calls.ll (added)
+++ llvm/trunk/test/Transforms/LoopVectorize/X86/svml-calls.ll Fri Jul 29 11:42:44 2016
@@ -0,0 +1,185 @@
+; RUN: opt -vector-library=SVML -loop-vectorize -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; CHECK-LABEL: @sin_f32
+; CHECK: <4 x float> @__svml_sinf4
+; CHECK: ret
+
+declare float @sinf(float) #0
+
+define void @sin_f32(float* nocapture %varray) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %tmp = trunc i64 %indvars.iv to i32
+ %conv = sitofp i32 %tmp to float
+ %call = tail call fast float @sinf(float %conv)
+ %arrayidx = getelementptr inbounds float, float* %varray, i64 %indvars.iv
+ store float %call, float* %arrayidx, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond = icmp eq i64 %indvars.iv.next, 1000
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+; CHECK-LABEL: @cos_f32
+; CHECK: <4 x float> @__svml_cosf4
+; CHECK: ret
+
+declare float @cosf(float) #0
+
+define void @cos_f32(float* nocapture %varray) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %tmp = trunc i64 %indvars.iv to i32
+ %conv = sitofp i32 %tmp to float
+ %call = tail call fast float @cosf(float %conv)
+ %arrayidx = getelementptr inbounds float, float* %varray, i64 %indvars.iv
+ store float %call, float* %arrayidx, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond = icmp eq i64 %indvars.iv.next, 1000
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+; CHECK-LABEL: @exp_f32
+; CHECK: <4 x float> @__svml_expf4
+; CHECK: ret
+
+declare float @expf(float) #0
+
+define void @exp_f32(float* nocapture %varray) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %tmp = trunc i64 %indvars.iv to i32
+ %conv = sitofp i32 %tmp to float
+ %call = tail call fast float @expf(float %conv)
+ %arrayidx = getelementptr inbounds float, float* %varray, i64 %indvars.iv
+ store float %call, float* %arrayidx, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond = icmp eq i64 %indvars.iv.next, 1000
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+; CHECK-LABEL: @exp_f32_intrin
+; CHECK: <4 x float> @__svml_expf4
+; CHECK: ret
+
+declare float @llvm.exp.f32(float) #0
+
+define void @exp_f32_intrin(float* nocapture %varray) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %tmp = trunc i64 %indvars.iv to i32
+ %conv = sitofp i32 %tmp to float
+ %call = tail call fast float @llvm.exp.f32(float %conv)
+ %arrayidx = getelementptr inbounds float, float* %varray, i64 %indvars.iv
+ store float %call, float* %arrayidx, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond = icmp eq i64 %indvars.iv.next, 1000
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+; CHECK-LABEL: @log_f32
+; CHECK: <4 x float> @__svml_logf4
+; CHECK: ret
+
+declare float @logf(float) #0
+
+define void @log_f32(float* nocapture %varray) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %tmp = trunc i64 %indvars.iv to i32
+ %conv = sitofp i32 %tmp to float
+ %call = tail call fast float @logf(float %conv)
+ %arrayidx = getelementptr inbounds float, float* %varray, i64 %indvars.iv
+ store float %call, float* %arrayidx, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond = icmp eq i64 %indvars.iv.next, 1000
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+; CHECK-LABEL: @pow_f32
+; CHECK: <4 x float> @__svml_powf4
+; CHECK: ret
+
+declare float @powf(float, float) #0
+
+define void @pow_f32(float* nocapture %varray, float* nocapture readonly %exp) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %tmp = trunc i64 %indvars.iv to i32
+ %conv = sitofp i32 %tmp to float
+ %arrayidx = getelementptr inbounds float, float* %exp, i64 %indvars.iv
+ %tmp1 = load float, float* %arrayidx, align 4
+ %tmp2 = tail call fast float @powf(float %conv, float %tmp1)
+ %arrayidx2 = getelementptr inbounds float, float* %varray, i64 %indvars.iv
+ store float %tmp2, float* %arrayidx2, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond = icmp eq i64 %indvars.iv.next, 1000
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+; CHECK-LABEL: @pow_f32_intrin
+; CHECK: <4 x float> @__svml_powf4
+; CHECK: ret
+
+declare float @llvm.pow.f32(float, float) #0
+
+define void @pow_f32_intrin(float* nocapture %varray, float* nocapture readonly %exp) {
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+ %tmp = trunc i64 %indvars.iv to i32
+ %conv = sitofp i32 %tmp to float
+ %arrayidx = getelementptr inbounds float, float* %exp, i64 %indvars.iv
+ %tmp1 = load float, float* %arrayidx, align 4
+ %tmp2 = tail call fast float @llvm.pow.f32(float %conv, float %tmp1)
+ %arrayidx2 = getelementptr inbounds float, float* %varray, i64 %indvars.iv
+ store float %tmp2, float* %arrayidx2, align 4
+ %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+ %exitcond = icmp eq i64 %indvars.iv.next, 1000
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body
+ ret void
+}
+
+attributes #0 = { nounwind readnone }
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