[llvm] r277007 - [AArch64][GlobalISel] Select G_BR.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 28 10:15:16 PDT 2016
Author: ab
Date: Thu Jul 28 12:15:15 2016
New Revision: 277007
URL: http://llvm.org/viewvc/llvm-project?rev=277007&view=rev
Log:
[AArch64][GlobalISel] Select G_BR.
This is the first unsized instruction we support; move down the
'sized' check to binops.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=277007&r1=277006&r2=277007&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Jul 28 12:15:15 2016
@@ -102,22 +102,27 @@ bool AArch64InstructionSelector::select(
LLT Ty = I.getType();
assert(Ty.isValid() && "Generic instruction doesn't have a type");
- // FIXME: Support unsized instructions (e.g., G_BR).
- if (!Ty.isSized()) {
- DEBUG(dbgs() << "Unsized generic instructions are unsupported\n");
- return false;
+ switch (I.getOpcode()) {
+ case TargetOpcode::G_BR: {
+ I.setDesc(TII.get(AArch64::B));
+ I.removeTypes();
+ return true;
}
- // The size (in bits) of the operation, or 0 for the label type.
- const unsigned OpSize = Ty.getSizeInBits();
-
- switch (I.getOpcode()) {
case TargetOpcode::G_OR:
case TargetOpcode::G_AND:
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB: {
DEBUG(dbgs() << "AArch64: Selecting: binop\n");
+ if (!Ty.isSized()) {
+ DEBUG(dbgs() << "Generic binop should be sized\n");
+ return false;
+ }
+
+ // The size (in bits) of the operation, or 0 for the label type.
+ const unsigned OpSize = Ty.getSizeInBits();
+
// Reject the various things we don't support yet.
{
const RegisterBank *PrevOpBank = nullptr;
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=277007&r1=277006&r2=277007&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Thu Jul 28 12:15:15 2016
@@ -20,6 +20,8 @@
define void @and_s32_gpr() { ret void }
define void @and_s64_gpr() { ret void }
+ define void @unconditional_br() { ret void }
+
...
---
@@ -214,3 +216,19 @@ body: |
%0(64) = COPY %x0
%1(64) = G_AND s64 %0, %0
...
+
+---
+# CHECK-LABEL: name: unconditional_br
+name: unconditional_br
+isSSA: true
+
+# CHECK: body:
+# CHECK: bb.0:
+# CHECK: successors: %bb.0
+# CHECK: B %bb.0
+body: |
+ bb.0:
+ successors: %bb.0
+
+ G_BR unsized %bb.0
+...
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