[llvm] r277002 - [AArch64][GlobalISel] Select GPR G_AND.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 28 09:58:31 PDT 2016
Author: ab
Date: Thu Jul 28 11:58:31 2016
New Revision: 277002
URL: http://llvm.org/viewvc/llvm-project?rev=277002&view=rev
Log:
[AArch64][GlobalISel] Select GPR G_AND.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=277002&r1=277001&r2=277002&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Jul 28 11:58:31 2016
@@ -52,6 +52,8 @@ static unsigned selectBinaryOp(unsigned
switch (GenericOpc) {
case TargetOpcode::G_OR:
return AArch64::ORRWrr;
+ case TargetOpcode::G_AND:
+ return AArch64::ANDWrr;
case TargetOpcode::G_ADD:
return AArch64::ADDWrr;
default:
@@ -61,6 +63,8 @@ static unsigned selectBinaryOp(unsigned
switch (GenericOpc) {
case TargetOpcode::G_OR:
return AArch64::ORRXrr;
+ case TargetOpcode::G_AND:
+ return AArch64::ANDXrr;
case TargetOpcode::G_ADD:
return AArch64::ADDXrr;
default:
@@ -105,6 +109,7 @@ bool AArch64InstructionSelector::select(
switch (I.getOpcode()) {
case TargetOpcode::G_OR:
+ case TargetOpcode::G_AND:
case TargetOpcode::G_ADD: {
DEBUG(dbgs() << "AArch64: Selecting: binop\n");
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=277002&r1=277001&r2=277002&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Thu Jul 28 11:58:31 2016
@@ -14,6 +14,9 @@
define void @or_s32_gpr() { ret void }
define void @or_s64_gpr() { ret void }
+ define void @and_s32_gpr() { ret void }
+ define void @and_s64_gpr() { ret void }
+
...
---
@@ -112,3 +115,51 @@ body: |
%0(64) = COPY %x0
%1(64) = G_OR s64 %0, %0
...
+
+---
+# Same as add_s32_gpr, for G_AND operations.
+# CHECK-LABEL: name: and_s32_gpr
+name: and_s32_gpr
+isSSA: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %w0
+# CHECK: %1 = ANDWrr %0, %0
+body: |
+ bb.0:
+ liveins: %w0
+
+ %0(32) = COPY %w0
+ %1(32) = G_AND s32 %0, %0
+...
+
+---
+# Same as add_s64_gpr, for G_AND operations.
+# CHECK-LABEL: name: and_s64_gpr
+name: and_s64_gpr
+isSSA: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr64 }
+# CHECK-NEXT: - { id: 1, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+
+# CHECK: body:
+# CHECK: %0 = COPY %x0
+# CHECK: %1 = ANDXrr %0, %0
+body: |
+ bb.0:
+ liveins: %x0
+
+ %0(64) = COPY %x0
+ %1(64) = G_AND s64 %0, %0
+...
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