[llvm] r276997 - TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFC
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 28 09:32:22 PDT 2016
Author: sjoerdmeijer
Date: Thu Jul 28 11:32:22 2016
New Revision: 276997
URL: http://llvm.org/viewvc/llvm-project?rev=276997&view=rev
Log:
TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFC
Differential Revision: https://reviews.llvm.org/D22925
Modified:
llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
llvm/trunk/lib/Target/ARM/README-Thumb.txt
llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp Thu Jul 28 11:32:22 2016
@@ -177,7 +177,7 @@ void AArch64BranchRelaxation::scanFuncti
void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
unsigned Size = 0;
for (const MachineInstr &MI : MBB)
- Size += TII->GetInstSizeInBytes(MI);
+ Size += TII->getInstSizeInBytes(MI);
BlockInfo[MBB.getNumber()].Size = Size;
}
@@ -195,7 +195,7 @@ unsigned AArch64BranchRelaxation::getIns
// Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
- Offset += TII->GetInstSizeInBytes(*I);
+ Offset += TII->getInstSizeInBytes(*I);
}
return Offset;
}
@@ -420,7 +420,7 @@ bool AArch64BranchRelaxation::fixupCondi
MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI);
// No need for the branch to the next block. We're adding an unconditional
// branch to the destination.
- int delta = TII->GetInstSizeInBytes(MBB->back());
+ int delta = TII->getInstSizeInBytes(MBB->back());
BlockInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent();
// BlockInfo[SplitBB].Offset is wrong temporarily, fixed below
@@ -446,12 +446,12 @@ bool AArch64BranchRelaxation::fixupCondi
if (MI->getOpcode() == AArch64::Bcc)
invertBccCondition(MIB);
MIB.addMBB(NextBB);
- BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
+ BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
- BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
+ BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
// Remove the old conditional branch. It may or may not still be in MBB.
- BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
+ BlockInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
MI->eraseFromParent();
// Finally, keep the block offsets up to date.
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Thu Jul 28 11:32:22 2016
@@ -38,7 +38,7 @@ AArch64InstrInfo::AArch64InstrInfo(const
/// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes.
-unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
+unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
const MachineBasicBlock &MBB = *MI.getParent();
const MachineFunction *MF = MBB.getParent();
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
@@ -58,7 +58,7 @@ unsigned AArch64InstrInfo::GetInstSizeIn
return 0;
}
- llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
+ llvm_unreachable("getInstSizeInBytes()- Unable to determin insn size");
}
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Thu Jul 28 11:32:22 2016
@@ -39,7 +39,7 @@ public:
/// always be able to get register info as well (through this method).
const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
- unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
+ unsigned getInstSizeInBytes(const MachineInstr &MI) const;
bool isAsCheapAsAMove(const MachineInstr &MI) const override;
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jul 28 11:32:22 2016
@@ -610,7 +610,7 @@ template <> bool IsCPSRDead<MachineInstr
/// GetInstSize - Return the size of the specified MachineInstr.
///
-unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
+unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
const MachineBasicBlock &MBB = *MI.getParent();
const MachineFunction *MF = MBB.getParent();
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
@@ -669,7 +669,7 @@ unsigned ARMBaseInstrInfo::getInstBundle
MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
while (++I != E && I->isInsideBundle()) {
assert(!I->isBundle() && "No nested bundle!");
- Size += GetInstSizeInBytes(*I);
+ Size += getInstSizeInBytes(*I);
}
return Size;
}
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Jul 28 11:32:22 2016
@@ -154,7 +154,7 @@ public:
/// GetInstSize - Returns the size of the specified MachineInstr.
///
- virtual unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
+ virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const;
unsigned isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
Modified: llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp Thu Jul 28 11:32:22 2016
@@ -42,8 +42,8 @@ void computeBlockSize(MachineFunction *M
BBI.PostAlign = 0;
for (MachineInstr &I : *MBB) {
- BBI.Size += TII->GetInstSizeInBytes(I);
- // For inline asm, GetInstSizeInBytes returns a conservative estimate.
+ BBI.Size += TII->getInstSizeInBytes(I);
+ // For inline asm, getInstSizeInBytes returns a conservative estimate.
// The actual size may be smaller, but still a multiple of the instr size.
if (I.isInlineAsm())
BBI.Unalign = isThumb ? 1 : 2;
Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Thu Jul 28 11:32:22 2016
@@ -823,7 +823,7 @@ unsigned ARMConstantIslands::getOffsetOf
// Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
- Offset += TII->GetInstSizeInBytes(*I);
+ Offset += TII->getInstSizeInBytes(*I);
}
return Offset;
}
@@ -1331,7 +1331,7 @@ void ARMConstantIslands::createNewWater(
// iterates at least once.
BaseInsertOffset =
std::max(UserBBI.postOffset() - UPad - 8,
- UserOffset + TII->GetInstSizeInBytes(*UserMI) + 1);
+ UserOffset + TII->getInstSizeInBytes(*UserMI) + 1);
DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
}
unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
@@ -1341,9 +1341,9 @@ void ARMConstantIslands::createNewWater(
unsigned CPUIndex = CPUserIndex+1;
unsigned NumCPUsers = CPUsers.size();
MachineInstr *LastIT = nullptr;
- for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI);
+ for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
Offset < BaseInsertOffset;
- Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) {
+ Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
assert(MI != UserMBB->end() && "Fell off end of block");
if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) {
CPUser &U = CPUsers[CPUIndex];
@@ -1644,7 +1644,7 @@ ARMConstantIslands::fixupConditionalBr(I
splitBlockBeforeInstr(MI);
// No need for the branch to the next block. We're adding an unconditional
// branch to the destination.
- int delta = TII->GetInstSizeInBytes(MBB->back());
+ int delta = TII->getInstSizeInBytes(MBB->back());
BBInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent();
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below
@@ -1660,18 +1660,18 @@ ARMConstantIslands::fixupConditionalBr(I
BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
.addMBB(NextBB).addImm(CC).addReg(CCReg);
Br.MI = &MBB->back();
- BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
+ BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
if (isThumb)
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
.addImm(ARMCC::AL).addReg(0);
else
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
- BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
+ BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
// Remove the old conditional branch. It may or may not still be in MBB.
- BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
+ BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
MI->eraseFromParent();
adjustBBOffsetsAfter(MBB);
return true;
@@ -2084,8 +2084,8 @@ bool ARMConstantIslands::optimizeThumb2J
}
}
- unsigned NewSize = TII->GetInstSizeInBytes(*NewJTMI);
- unsigned OrigSize = TII->GetInstSizeInBytes(*MI);
+ unsigned NewSize = TII->getInstSizeInBytes(*NewJTMI);
+ unsigned OrigSize = TII->getInstSizeInBytes(*MI);
MI->eraseFromParent();
int Delta = OrigSize - NewSize + DeadSize;
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jul 28 11:32:22 2016
@@ -1359,7 +1359,7 @@ static unsigned GetFunctionSizeInBytes(c
unsigned FnSize = 0;
for (auto &MBB : MF) {
for (auto &MI : MBB)
- FnSize += TII.GetInstSizeInBytes(MI);
+ FnSize += TII.getInstSizeInBytes(MI);
}
return FnSize;
}
Modified: llvm/trunk/lib/Target/ARM/README-Thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README-Thumb.txt?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/README-Thumb.txt (original)
+++ llvm/trunk/lib/Target/ARM/README-Thumb.txt Thu Jul 28 11:32:22 2016
@@ -238,7 +238,7 @@ Thumb2.
//===---------------------------------------------------------------------===//
Rather than having tBR_JTr print a ".align 2" and constant island pass pad it,
-add a target specific ALIGN instruction instead. That way, GetInstSizeInBytes
+add a target specific ALIGN instruction instead. That way, getInstSizeInBytes
won't have to over-estimate. It can also be used for loop alignment pass.
//===---------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp Thu Jul 28 11:32:22 2016
@@ -439,7 +439,7 @@ bool AVRInstrInfo::ReverseBranchConditio
return false;
}
-unsigned AVRInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
+unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
unsigned Opcode = MI->getOpcode();
switch (Opcode) {
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.h?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.h Thu Jul 28 11:32:22 2016
@@ -70,7 +70,7 @@ public:
const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
- unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
+ unsigned getInstSizeInBytes(const MachineInstr *MI) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
Modified: llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp Thu Jul 28 11:32:22 2016
@@ -70,7 +70,7 @@ bool MSP430BSel::runOnMachineFunction(Ma
for (MachineBasicBlock &MBB : Fn) {
unsigned BlockSize = 0;
for (MachineInstr &MI : MBB)
- BlockSize += TII->GetInstSizeInBytes(MI);
+ BlockSize += TII->getInstSizeInBytes(MI);
BlockSizes[MBB.getNumber()] = BlockSize;
FuncSize += BlockSize;
@@ -107,7 +107,7 @@ bool MSP430BSel::runOnMachineFunction(Ma
I != E; ++I) {
if ((I->getOpcode() != MSP430::JCC || I->getOperand(0).isImm()) &&
I->getOpcode() != MSP430::JMP) {
- MBBStartOffset += TII->GetInstSizeInBytes(*I);
+ MBBStartOffset += TII->getInstSizeInBytes(*I);
continue;
}
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Thu Jul 28 11:32:22 2016
@@ -293,7 +293,7 @@ unsigned MSP430InstrInfo::InsertBranch(M
/// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes.
///
-unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
+unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
const MCInstrDesc &Desc = MI.getDesc();
switch (Desc.TSFlags & MSP430II::SizeMask) {
Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Thu Jul 28 11:32:22 2016
@@ -68,7 +68,7 @@ public:
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
- unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
+ unsigned getInstSizeInBytes(const MachineInstr &MI) const;
// Branch folding goodness
bool
Modified: llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp Thu Jul 28 11:32:22 2016
@@ -801,7 +801,7 @@ void MipsConstantIslands::computeBlockSi
BBI.Size = 0;
for (const MachineInstr &MI : *MBB)
- BBI.Size += TII->GetInstSizeInBytes(MI);
+ BBI.Size += TII->getInstSizeInBytes(MI);
}
/// getOffsetOf - Return the current offset of the specified machine instruction
@@ -818,7 +818,7 @@ unsigned MipsConstantIslands::getOffsetO
// Sum instructions before MI in MBB.
for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
- Offset += TII->GetInstSizeInBytes(*I);
+ Offset += TII->getInstSizeInBytes(*I);
}
return Offset;
}
@@ -1297,9 +1297,9 @@ void MipsConstantIslands::createNewWater
unsigned CPUIndex = CPUserIndex+1;
unsigned NumCPUsers = CPUsers.size();
//MachineInstr *LastIT = 0;
- for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI);
+ for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
Offset < BaseInsertOffset;
- Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) {
+ Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
assert(MI != UserMBB->end() && "Fell off end of block");
if (CPUIndex < NumCPUsers &&
CPUsers[CPUIndex].MI == static_cast<MachineInstr *>(MI)) {
@@ -1622,7 +1622,7 @@ MipsConstantIslands::fixupConditionalBr(
splitBlockBeforeInstr(*MI);
// No need for the branch to the next block. We're adding an unconditional
// branch to the destination.
- int delta = TII->GetInstSizeInBytes(MBB->back());
+ int delta = TII->getInstSizeInBytes(MBB->back());
BBInfo[MBB->getNumber()].Size -= delta;
MBB->back().eraseFromParent();
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below
@@ -1644,14 +1644,14 @@ MipsConstantIslands::fixupConditionalBr(
.addMBB(NextBB);
}
Br.MI = &MBB->back();
- BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
+ BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
- BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
+ BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
// Remove the old conditional branch. It may or may not still be in MBB.
- BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
+ BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
MI->eraseFromParent();
adjustBBOffsetsAfter(MBB);
return true;
Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Thu Jul 28 11:32:22 2016
@@ -602,7 +602,7 @@ bool Filler::runOnMachineBasicBlock(Mach
// Get instruction with delay slot.
MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
- if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 &&
+ if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
DSI->isCall()) {
// If instruction in delay slot is 16b change opcode to
// corresponding instruction with short delay slot.
@@ -692,7 +692,7 @@ bool Filler::searchRange(MachineBasicBlo
bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo();
unsigned Opcode = (*Slot).getOpcode();
- if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 &&
+ if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
(Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
Opcode == Mips::PseudoReturn))
continue;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Jul 28 11:32:22 2016
@@ -398,7 +398,7 @@ bool MipsInstrInfo::HasForbiddenSlot(con
}
/// Return the number of bytes of code the specified instruction may be.
-unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
+unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
return MI.getDesc().getSize();
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Thu Jul 28 11:32:22 2016
@@ -92,7 +92,7 @@ public:
virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
/// Return the number of bytes of code the specified instruction may be.
- unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
+ unsigned getInstSizeInBytes(const MachineInstr &MI) const;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
Modified: llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp Thu Jul 28 11:32:22 2016
@@ -179,7 +179,7 @@ void MipsLongBranch::initMBBInfo() {
// Compute size of MBB.
for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
MI != MBB->instr_end(); ++MI)
- MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI);
+ MBBInfos[I].Size += TII->getInstSizeInBytes(*MI);
// Search for MBB's branch instruction.
ReverseIter End = MBB->rend();
Modified: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp Thu Jul 28 11:32:22 2016
@@ -108,7 +108,7 @@ bool PPCBSel::runOnMachineFunction(Machi
unsigned BlockSize = 0;
for (MachineInstr &MI : *MBB)
- BlockSize += TII->GetInstSizeInBytes(MI);
+ BlockSize += TII->getInstSizeInBytes(MI);
BlockSizes[MBB->getNumber()] = BlockSize;
FuncSize += BlockSize;
@@ -155,7 +155,7 @@ bool PPCBSel::runOnMachineFunction(Machi
Dest = I->getOperand(0).getMBB();
if (!Dest) {
- MBBStartOffset += TII->GetInstSizeInBytes(*I);
+ MBBStartOffset += TII->getInstSizeInBytes(*I);
continue;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jul 28 11:32:22 2016
@@ -11243,7 +11243,7 @@ unsigned PPCTargetLowering::getPrefLoopA
uint64_t LoopSize = 0;
for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) {
- LoopSize += TII->GetInstSizeInBytes(*J);
+ LoopSize += TII->getInstSizeInBytes(*J);
if (LoopSize > 32)
break;
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Jul 28 11:32:22 2016
@@ -1808,7 +1808,7 @@ bool PPCInstrInfo::optimizeCompareInstr(
/// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes.
///
-unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
+unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
unsigned Opcode = MI.getOpcode();
if (Opcode == PPC::INLINEASM) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=276997&r1=276996&r2=276997&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Thu Jul 28 11:32:22 2016
@@ -256,7 +256,7 @@ public:
/// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes.
///
- unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
+ unsigned getInstSizeInBytes(const MachineInstr &MI) const;
void getNoopForMachoTarget(MCInst &NopInst) const override;
More information about the llvm-commits
mailing list