[llvm] r276980 - AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling

[Tom Stellard via llvm-commits]

On Thu, Jul 28, 2016 at 02:30:43PM -0000, Tom Stellard via llvm-commits wrote:
> Author: tstellar
> Date: Thu Jul 28 09:30:43 2016
> New Revision: 276980
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=276980&view=rev
> Log:
> AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling
> 
> Summary:
> We were using reserved VGPRs for SGPR spilling and this was causing
> some programs with a workgroup size of 1024 to use more than 64
> registers, which is illegal.
> 
> Reviewers: arsenm, mareko, nhaehnle
> 
> Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl
> 

Hi Hans,

Is this OK to merge to the 3.9 branch?  I am the code owner, and I approve.

-Tom

> Differential Revision: https://reviews.llvm.org/D22032
> 
> Modified:
>     llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
>     llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
>     llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
>     llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
> 
> Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=276980&r1=276979&r2=276980&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Jul 28 09:30:43 2016
> @@ -738,7 +738,8 @@ unsigned SIInstrInfo::calculateLDSSpillA
>      MachineBasicBlock::iterator Insert = Entry.front();
>      DebugLoc DL = Insert->getDebugLoc();
>  
> -    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
> +    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
> +                                   *MF);
>      if (TIDReg == AMDGPU::NoRegister)
>        return TIDReg;
>  
> 
> Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=276980&r1=276979&r2=276980&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Thu Jul 28 09:30:43 2016
> @@ -210,7 +210,8 @@ SIMachineFunctionInfo::SpilledReg SIMach
>    Spill.Lane = Lane;
>  
>    if (!LaneVGPRs.count(LaneVGPRIdx)) {
> -    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
> +    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
> +                                                *MF);
>  
>      if (LaneVGPR == AMDGPU::NoRegister)
>        // We have no VGPRs left for spilling SGPRs.
> 
> Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=276980&r1=276979&r2=276980&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Jul 28 09:30:43 2016
> @@ -958,10 +958,13 @@ unsigned SIRegisterInfo::getPreloadedVal
>  /// \brief Returns a register that is not used at any point in the function.
>  ///        If all registers are used, then this function will return
>  //         AMDGPU::NoRegister.
> -unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
> -                                           const TargetRegisterClass *RC) const {
> +unsigned
> +SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
> +                                   const TargetRegisterClass *RC,
> +                                   const MachineFunction &MF) const {
> +
>    for (unsigned Reg : *RC)
> -    if (!MRI.isPhysRegUsed(Reg))
> +    if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg))
>        return Reg;
>    return AMDGPU::NoRegister;
>  }
> 
> Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h?rev=276980&r1=276979&r2=276980&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h Thu Jul 28 09:30:43 2016
> @@ -185,7 +185,8 @@ public:
>    unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;
>  
>    unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
> -                              const TargetRegisterClass *RC) const;
> +                              const TargetRegisterClass *RC,
> +                              const MachineFunction &MF) const;
>  
>    unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
>    unsigned getVGPR32PressureSet() const { return VGPR32SetID; };
> 
> 
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