[PATCH] D22032: AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL276980: AMDGPU/SI: Don't use reserved VGPRs for SGPR spilling (authored by tstellar).

Changed prior to commit:
  https://reviews.llvm.org/D22032?vs=64486&id=65932#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D22032

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h

Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -958,10 +958,13 @@
 /// \brief Returns a register that is not used at any point in the function.
 ///        If all registers are used, then this function will return
 //         AMDGPU::NoRegister.
-unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
-                                           const TargetRegisterClass *RC) const {
+unsigned
+SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
+                                   const TargetRegisterClass *RC,
+                                   const MachineFunction &MF) const {
+
   for (unsigned Reg : *RC)
-    if (!MRI.isPhysRegUsed(Reg))
+    if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg))
       return Reg;
   return AMDGPU::NoRegister;
 }
Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -185,7 +185,8 @@
   unsigned getNumSGPRsAllowed(const SISubtarget &ST, unsigned WaveCount) const;
 
   unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
-                              const TargetRegisterClass *RC) const;
+                              const TargetRegisterClass *RC,
+                              const MachineFunction &MF) const;
 
   unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
   unsigned getVGPR32PressureSet() const { return VGPR32SetID; };
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -738,7 +738,8 @@
     MachineBasicBlock::iterator Insert = Entry.front();
     DebugLoc DL = Insert->getDebugLoc();
 
-    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
+    TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
+                                   *MF);
     if (TIDReg == AMDGPU::NoRegister)
       return TIDReg;
 
Index: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -210,7 +210,8 @@
   Spill.Lane = Lane;
 
   if (!LaneVGPRs.count(LaneVGPRIdx)) {
-    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
+    unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
+                                                *MF);
 
     if (LaneVGPR == AMDGPU::NoRegister)
       // We have no VGPRs left for spilling SGPRs.


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