[PATCH] D22722: MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

[Duncan P. N. Exon Smith via llvm-commits]

I just had another thought: that computing isSSA instead of printing/parsing it could make "the current backend state" less reproducible.

Should there be an assert or error message during printing if isSSA is set incorrectly?  (Maybe the patch already does this...)

> On 2016-Jul-25, at 18:17, Duncan P. N. Exon Smith via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> This sounds obviously good from the description, but I'm on vacation and don't have time to look at the patch.  Anyone else care to have a peek?
> 
>> On 2016-Jul-23, at 00:00, Matthias Braun <matze at braunis.de> wrote:
>> 
>> MatzeB updated this revision to Diff 65213.
>> MatzeB added a comment.
>> 
>> Fix some bugs in the patch.
>> 
>> 
>> Repository:
>> rL LLVM
>> 
>> https://reviews.llvm.org/D22722
>> 
>> Files:
>> include/llvm/CodeGen/MIRYamlMapping.h
>> lib/CodeGen/MIRParser/MIRParser.cpp
>> lib/CodeGen/MIRPrinter.cpp
>> lib/CodeGen/MachineVerifier.cpp
>> test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
>> test/CodeGen/AArch64/GlobalISel/legalize-add.mir
>> test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
>> test/CodeGen/AArch64/movimm-wzr.mir
>> test/CodeGen/AMDGPU/detect-dead-lanes.mir
>> test/CodeGen/AMDGPU/rename-independent-subregs.mir
>> test/CodeGen/ARM/ARMLoadStoreDBG.mir
>> test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
>> test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
>> test/CodeGen/MIR/AArch64/machine-scheduler.mir
>> test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
>> test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
>> test/CodeGen/MIR/Generic/frame-info.mir
>> test/CodeGen/MIR/Generic/register-info.mir
>> test/CodeGen/MIR/Lanai/peephole-compare.mir
>> test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
>> test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
>> test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
>> test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
>> test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
>> test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
>> test/CodeGen/MIR/X86/function-liveins.mir
>> test/CodeGen/MIR/X86/generic-instr-type-error.mir
>> test/CodeGen/MIR/X86/generic-virtual-registers.mir
>> test/CodeGen/MIR/X86/instructions-debug-location.mir
>> test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
>> test/CodeGen/MIR/X86/metadata-operands.mir
>> test/CodeGen/MIR/X86/stack-object-debug-info.mir
>> test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
>> test/CodeGen/MIR/X86/stack-object-operands.mir
>> test/CodeGen/MIR/X86/standalone-register-error.mir
>> test/CodeGen/MIR/X86/subregister-index-operands.mir
>> test/CodeGen/MIR/X86/subregister-operands.mir
>> test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
>> test/CodeGen/MIR/X86/undefined-register-class.mir
>> test/CodeGen/MIR/X86/undefined-stack-object.mir
>> test/CodeGen/MIR/X86/undefined-virtual-register.mir
>> test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
>> test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
>> test/CodeGen/MIR/X86/unknown-metadata-node.mir
>> test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
>> test/CodeGen/MIR/X86/unknown-subregister-index.mir
>> test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
>> test/CodeGen/MIR/X86/virtual-registers.mir
>> test/CodeGen/PowerPC/aantidep-def-ec.mir
>> test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
>> test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
>> test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
>> test/CodeGen/X86/eflags-copy-expansion.mir
>> test/CodeGen/X86/fixup-bw-copy.mir
>> test/CodeGen/X86/implicit-null-checks.mir
>> test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
>> test/DebugInfo/MIR/X86/live-debug-values.mir
>> 
>> <D22722.65213.patch>
> 
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