[llvm] r276773 - [Hexagon] Add support for proper handling of H and L constraints
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 26 10:31:02 PDT 2016
Author: kparzysz
Date: Tue Jul 26 12:31:02 2016
New Revision: 276773
URL: http://llvm.org/viewvc/llvm-project?rev=276773&view=rev
Log:
[Hexagon] Add support for proper handling of H and L constraints
H -> High part of reg pair.
L -> Low part of reg pair.
Patch by Sundeep Kushwaha.
Added:
llvm/trunk/test/CodeGen/Hexagon/inline-asm-hexagon.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=276773&r1=276772&r2=276773&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Tue Jul 26 12:31:02 2016
@@ -81,7 +81,7 @@ HexagonAsmPrinter::HexagonAsmPrinter(Tar
: AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr) {}
void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
- raw_ostream &O) {
+ raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
@@ -141,14 +141,22 @@ bool HexagonAsmPrinter::PrintAsmOperand(
// Hexagon never has a prefix.
printOperand(MI, OpNo, OS);
return false;
- case 'L': // Write second word of DImode reference.
- // Verify that this operand has two consecutive registers.
- if (!MI->getOperand(OpNo).isReg() ||
- OpNo+1 == MI->getNumOperands() ||
- !MI->getOperand(OpNo+1).isReg())
+ case 'L':
+ case 'H': { // The highest-numbered register of a pair.
+ const MachineOperand &MO = MI->getOperand(OpNo);
+ const MachineFunction &MF = *MI->getParent()->getParent();
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+ if (!MO.isReg())
return true;
- ++OpNo; // Return the high-part.
- break;
+ unsigned RegNumber = MO.getReg();
+ // This should be an assert in the frontend.
+ if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
+ RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
+ Hexagon::subreg_loreg :
+ Hexagon::subreg_hireg);
+ OS << HexagonInstPrinter::getRegisterName(RegNumber);
+ return false;
+ }
case 'I':
// Write 'i' if an integer constant, otherwise nothing. Used to print
// addi vs add, etc.
Added: llvm/trunk/test/CodeGen/Hexagon/inline-asm-hexagon.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/inline-asm-hexagon.ll?rev=276773&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/inline-asm-hexagon.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/inline-asm-hexagon.ll Tue Jul 26 12:31:02 2016
@@ -0,0 +1,16 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target triple = "hexagon"
+
+;CHECK: [[REGH:r[0-9]]]:[[REGL:[0-9]]] = memd_locked
+;CHECK: HIGH([[REGH]])
+;CHECK: LOW(r[[REGL]])
+define i32 @fred(i64* %free_list_ptr, i32** %item_ptr, i8** %free_item_ptr) nounwind {
+entry:
+ %free_list_ptr.addr = alloca i64*, align 4
+ store i64* %free_list_ptr, i64** %free_list_ptr.addr, align 4
+ %0 = load i32*, i32** %item_ptr, align 4
+ %1 = call { i64, i32 } asm sideeffect "1: $0 = memd_locked($5)\0A\09 $1 = HIGH(${0:H}) \0A\09 $1 = add($1,#1) \0A\09 memw($6) = LOW(${0:L}) \0A\09 $0 = combine($7,$1) \0A\09 memd_locked($5,p0) = $0 \0A\09 if !p0 jump 1b\0A\09", "=&r,=&r,=*m,=*m,r,r,r,r,*m,*m,~{p0}"(i64** %free_list_ptr.addr, i8** %free_item_ptr, i64 0, i64* %free_list_ptr, i8** %free_item_ptr, i32* %0, i64** %free_list_ptr.addr, i8** %free_item_ptr) nounwind
+ %asmresult1 = extractvalue { i64, i32 } %1, 1
+ ret i32 %asmresult1
+}
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