[llvm] r276739 - [mips] MIPS64R6 compact branch support
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 26 03:25:07 PDT 2016
Author: sdardis
Date: Tue Jul 26 05:25:07 2016
New Revision: 276739
URL: http://llvm.org/viewvc/llvm-project?rev=276739&view=rev
Log:
[mips] MIPS64R6 compact branch support
MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct
MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that
map to the same instruction, extend compact branch support for the
corresponding 64bit branches.
Reviewers: dsanders
Differential Revision: https://reviews.llvm.org/D20164
Added:
llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
Modified:
llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/trunk/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=276739&r1=276738&r2=276739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Tue Jul 26 05:25:07 2016
@@ -3720,7 +3720,14 @@ unsigned MipsAsmParser::checkTargetMatch
case Mips::BLTZC:
case Mips::BEQZC:
case Mips::BNEZC:
- if (Inst.getOperand(0).getReg() == Mips::ZERO)
+ case Mips::BLEZC64:
+ case Mips::BGEZC64:
+ case Mips::BGTZC64:
+ case Mips::BLTZC64:
+ case Mips::BEQZC64:
+ case Mips::BNEZC64:
+ if (Inst.getOperand(0).getReg() == Mips::ZERO ||
+ Inst.getOperand(0).getReg() == Mips::ZERO_64)
return Match_RequiresNoZeroRegister;
return Match_Success;
case Mips::BGEC:
@@ -3729,9 +3736,17 @@ unsigned MipsAsmParser::checkTargetMatch
case Mips::BLTUC:
case Mips::BEQC:
case Mips::BNEC:
- if (Inst.getOperand(0).getReg() == Mips::ZERO)
+ case Mips::BGEC64:
+ case Mips::BLTC64:
+ case Mips::BGEUC64:
+ case Mips::BLTUC64:
+ case Mips::BEQC64:
+ case Mips::BNEC64:
+ if (Inst.getOperand(0).getReg() == Mips::ZERO ||
+ Inst.getOperand(0).getReg() == Mips::ZERO_64)
return Match_RequiresNoZeroRegister;
- if (Inst.getOperand(1).getReg() == Mips::ZERO)
+ if (Inst.getOperand(1).getReg() == Mips::ZERO ||
+ Inst.getOperand(1).getReg() == Mips::ZERO_64)
return Match_RequiresNoZeroRegister;
if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
return Match_RequiresDifferentOperands;
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp?rev=276739&r1=276738&r2=276739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp Tue Jul 26 05:25:07 2016
@@ -129,7 +129,8 @@ void MipsMCCodeEmitter::LowerCompactBran
unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
- if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC) {
+ if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
+ Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
if (Reg0 < Reg1)
return;
@@ -141,7 +142,7 @@ void MipsMCCodeEmitter::LowerCompactBran
if (Reg1 >= Reg0)
return;
} else
- llvm_unreachable("Cannot rewrite unknown branch!");
+ llvm_unreachable("Cannot rewrite unknown branch!");
Inst.getOperand(0).setReg(RegOp1);
Inst.getOperand(1).setReg(RegOp0);
@@ -210,6 +211,8 @@ encodeInstruction(const MCInst &MI, raw_
// Compact branches, enforce encoding restrictions.
case Mips::BEQC:
case Mips::BNEC:
+ case Mips::BEQC64:
+ case Mips::BNEC64:
case Mips::BOVC:
case Mips::BOVC_MMR6:
case Mips::BNVC:
Modified: llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td?rev=276739&r1=276738&r2=276739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td Tue Jul 26 05:25:07 2016
@@ -76,6 +76,19 @@ class SCD_R6_DESC : SC_R6_DESC_BASE<"s
class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
+class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
+class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
+class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
+class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
+class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
+class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
+class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
+class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
+class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
+class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
+class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;
+class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
+
class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
GPR64Opnd> {
bit isCall = 1;
@@ -130,10 +143,28 @@ let AdditionalPredicates = [NotInMicroMi
def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6;
def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6;
}
-let isCodeGenOnly = 1 in {
-def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6;
-def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6;
+
+let DecoderNamespace = "Mips32r6_64r6_GP64" in {
+// Jump and Branch Instructions
+def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
+def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
+
+def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
+def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
+def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
+def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
+def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
+def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
+def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64;
+def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;
+def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;
+def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;
+}
+let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {
+def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;
+def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;
}
+
//===----------------------------------------------------------------------===//
//
// Instruction Aliases
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=276739&r1=276738&r2=276739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Tue Jul 26 05:25:07 2016
@@ -341,6 +341,22 @@ unsigned MipsInstrInfo::getEquivalentCom
return Mips::BLTUC;
case Mips::BLTZ:
return Mips::BLTZC;
+ case Mips::BEQ64:
+ if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
+ return 0;
+ return Mips::BEQC64;
+ case Mips::BNE64:
+ if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
+ return 0;
+ return Mips::BNEC64;
+ case Mips::BGTZ64:
+ return Mips::BGTZC64;
+ case Mips::BGEZ64:
+ return Mips::BGEZC64;
+ case Mips::BLTZ64:
+ return Mips::BLTZC64;
+ case Mips::BLEZ64:
+ return Mips::BLEZC64;
// For MIPSR6, the instruction 'jic' can be used for these cases. Some
// tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
case Mips::JR:
@@ -403,7 +419,7 @@ MipsInstrInfo::genInstrWithNewOpc(unsign
MachineBasicBlock::iterator I) const {
MachineInstrBuilder MIB;
- // Certain branches have two forms: e.g beq $1, $zero, dst vs beqz $1, dest
+ // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
// Pick the zero form of the branch for readable assembly and for greater
// branch distance in non-microMIPS mode.
// FIXME: Certain atomic sequences on mips64 generate 32bit references to
@@ -429,6 +445,12 @@ MipsInstrInfo::genInstrWithNewOpc(unsign
case Mips::BLTC:
NewOpc = Mips::BLTZC;
break;
+ case Mips::BEQC64:
+ NewOpc = Mips::BEQZC64;
+ break;
+ case Mips::BNEC64:
+ NewOpc = Mips::BNEZC64;
+ break;
}
}
Modified: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp?rev=276739&r1=276738&r2=276739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp Tue Jul 26 05:25:07 2016
@@ -433,6 +433,18 @@ unsigned MipsSEInstrInfo::getOppositeBra
case Mips::BGEZC: return Mips::BLTZC;
case Mips::BLTZC: return Mips::BGEZC;
case Mips::BLEZC: return Mips::BGTZC;
+ case Mips::BEQZC64: return Mips::BNEZC64;
+ case Mips::BNEZC64: return Mips::BEQZC64;
+ case Mips::BEQC64: return Mips::BNEC64;
+ case Mips::BNEC64: return Mips::BEQC64;
+ case Mips::BGEC64: return Mips::BLTC64;
+ case Mips::BGEUC64: return Mips::BLTUC64;
+ case Mips::BLTC64: return Mips::BGEC64;
+ case Mips::BLTUC64: return Mips::BGEUC64;
+ case Mips::BGTZC64: return Mips::BLEZC64;
+ case Mips::BGEZC64: return Mips::BLTZC64;
+ case Mips::BLTZC64: return Mips::BGEZC64;
+ case Mips::BLEZC64: return Mips::BGTZC64;
}
}
@@ -518,8 +530,12 @@ unsigned MipsSEInstrInfo::getAnalyzableB
Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
- Opc == Mips::BEQZC || Opc == Mips::BNEZC ||
- Opc == Mips::BC) ? Opc : 0;
+ Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 ||
+ Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
+ Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
+ Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
+ Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
+ Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
}
void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
Modified: llvm/trunk/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll?rev=276739&r1=276738&r2=276739&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll Tue Jul 26 05:25:07 2016
@@ -1,4 +1,6 @@
; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
+; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s
+
; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
@@ -12,6 +14,7 @@
; may simplify out the crucical bnec $4, $4 instruction.
define internal void @_ZL14TestRemoveLastv(i32* %alist.sroa.0.4) {
+; CHECK-LABEL: _ZL14TestRemoveLastv:
entry:
%ascevgep = getelementptr i32, i32* %alist.sroa.0.4, i64 99
br label %do.body121
@@ -46,6 +49,43 @@ do.end146:
br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
}
+
+define internal void @_ZL14TestRemoveLastv64(i64* %alist.sroa.0.4) {
+; CHECK-LABEL: _ZL14TestRemoveLastv64:
+entry:
+ %ascevgep = getelementptr i64, i64* %alist.sroa.0.4, i64 99
+ br label %do.body121
+
+for.cond117:
+ %alsr.iv.next = add nsw i64 %alsr.iv, -1
+ %ascevgep340 = getelementptr i64, i64* %alsr.iv339, i64 -1
+ %acmp118 = icmp sgt i64 %alsr.iv.next, 0
+ br i1 %acmp118, label %do.body121, label %if.then143
+
+do.body121:
+ %alsr.iv339 = phi i64* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ]
+ %alsr.iv = phi i64 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ]
+ %a9 = add i64 %alsr.iv, -1
+ %alnot124 = icmp eq i64 %alsr.iv, %alsr.iv
+ br i1 %alnot124, label %do.body134, label %if.then143, !prof !11
+
+do.body134:
+ %a10 = add i64 %alsr.iv, -1
+ %a11 = load i64, i64* %alsr.iv339, align 4, !tbaa !5
+; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]]
+; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
+ %alnot137 = icmp eq i64 %a9, %a11
+ br i1 %alnot137, label %do.end146, label %if.then143, !prof !11
+
+if.then143:
+ ret void
+ unreachable
+
+do.end146:
+ %alnot151 = icmp eq i64 %a9, %a10
+ br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11
+
+}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C++ TBAA"}
!5 = !{!6, !6, i64 0}
Added: llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branches-64.ll?rev=276739&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branches-64.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branches-64.ll Tue Jul 26 05:25:07 2016
@@ -0,0 +1,194 @@
+; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define void @l() {
+entry:
+; CHECK-LABEL: l:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+; CHECK: jalrc $25
+ %call1 = tail call i64 @j()
+ %cmp = icmp eq i64 %call, %call1
+; CHECK: bnec
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry:
+; CHECK: jalrc $25
+ tail call void @f(i64 signext -2)
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+; CHECK: jrc $ra
+ ret void
+}
+
+declare i64 @k()
+
+declare i64 @j()
+
+declare void @f(i64 signext)
+
+; Function Attrs: define void @l2() {
+define void @l2() {
+entry:
+; CHECK-LABEL: l2:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+; CHECK: jalrc $25
+ %call1 = tail call i64 @i()
+ %cmp = icmp eq i64 %call, %call1
+; CHECK: beqc
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry:
+; CHECK: jalrc $25
+ tail call void @f(i64 signext -1)
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+; CHECK: jrc $ra
+ ret void
+}
+
+declare i64 @i()
+
+; Function Attrs: nounwind
+define void @l3() {
+entry:
+; CHECK-LABEL: l3:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+ %cmp = icmp slt i64 %call, 0
+; CHECK: bgez
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry:
+; CHECK: jalrc $25
+ tail call void @f(i64 signext 0)
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+; CHECK: jrc $ra
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @l4() {
+entry:
+; CHECK-LABEL: l4:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+ %cmp = icmp slt i64 %call, 1
+; CHECK: bgtzc
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry:
+ tail call void @f(i64 signext 1)
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+; CHECK: jrc $ra
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @l5() {
+entry:
+; CHECK-LABEL: l5:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+ %cmp = icmp sgt i64 %call, 0
+; CHECK: blezc
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry:
+; CHECK: jalrc $25
+ tail call void @f(i64 signext 2)
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+; CHECK: jrc $ra
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @l6() {
+entry:
+; CHECK-LABEL: l6:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+ %cmp = icmp sgt i64 %call, -1
+; CHECK: bltzc
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry:
+; CHECK: jalrc $25
+ tail call void @f(i64 signext 3)
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+; CHECK: jrc $ra
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @l7() {
+entry:
+; CHECK-LABEL: l7:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+ %cmp = icmp eq i64 %call, 0
+; CHECK: bnezc
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry:
+; CHECK: jalrc $25
+ tail call void @f(i64 signext 4)
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+; CHECK: jrc $ra
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @l8() {
+entry:
+; CHECK-LABEL: l8:
+; CHECK: jalrc $25
+ %call = tail call i64 @k()
+ %cmp = icmp eq i64 %call, 0
+; CHECK: beqzc
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then: ; preds = %entry:
+; CHECK: jalrc $25
+ tail call void @f(i64 signext 5)
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+; CHECK: jrc $ra
+ ret void
+}
+
+define i64 @l9(i8* ()* %i) {
+entry:
+; CHECK-LABEL: l9:
+ %i.addr = alloca i8* ()*, align 4
+ store i8* ()* %i, i8* ()** %i.addr, align 4
+; CHECK: jalrc $25
+ %call = call i64 @k()
+ %cmp = icmp ne i64 %call, 0
+; CHECK: beqzc
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ %0 = load i8* ()*, i8* ()** %i.addr, align 4
+; CHECK: jalrc $25
+ %call1 = call i8* %0()
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+; CHECK: jrc $ra
+ ret i64 -1
+}
Modified: llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll?rev=276739&r1=276738&r2=276739&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll Tue Jul 26 05:25:07 2016
@@ -1,11 +1,14 @@
-; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s \
-; RUN: -filetype=obj -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
+; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
+; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
+; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
+; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
; bnezc and beqzc have restriction that $rt != 0
define i32 @f() {
-; CHECK-LABEL: f
+; CHECK-LABEL: f:
; CHECK-NOT: bnezc $0
%cmp = icmp eq i32 1, 1
@@ -19,7 +22,7 @@ define i32 @f() {
}
define i32 @f1() {
-; CHECK-LABEL: f1
+; CHECK-LABEL: f1:
; CHECK-NOT: beqzc $0
%cmp = icmp eq i32 0, 0
@@ -37,7 +40,7 @@ define i32 @f1() {
; beqc and bnec have the restriction that $rs < $rt.
define i32 @f2(i32 %a, i32 %b) {
-; ENCODING-LABEL: f2
+; ENCODING-LABEL: f2:
; ENCODING-NOT: beqc $5, $4
; ENCODING-NOT: bnec $5, $4
@@ -51,3 +54,49 @@ define i32 @f2(i32 %a, i32 %b) {
ret i32 0
}
+define i64 @f3() {
+; CHECK-LABEL: f3:
+; CHECK-NOT: bnezc $0
+
+ %cmp = icmp eq i64 1, 1
+ br i1 %cmp, label %if.then, label %if.end
+
+ if.then:
+ ret i64 1
+
+ if.end:
+ ret i64 0
+}
+
+define i64 @f4() {
+; CHECK-LABEL: f4:
+; CHECK-NOT: beqzc $0
+
+ %cmp = icmp eq i64 0, 0
+ br i1 %cmp, label %if.then, label %if.end
+
+ if.then:
+ ret i64 1
+
+ if.end:
+ ret i64 0
+}
+
+; We silently fixup cases where the register allocator or user has given us
+; an instruction with incorrect operands that is trivially acceptable.
+; beqc and bnec have the restriction that $rs < $rt.
+
+define i64 @f5(i64 %a, i64 %b) {
+; ENCODING-LABEL: f5:
+; ENCODING-NOT: beqc $5, $4
+; ENCODING-NOT: bnec $5, $4
+
+ %cmp = icmp eq i64 %b, %a
+ br i1 %cmp, label %if.then, label %if.end
+
+ if.then:
+ ret i64 1
+
+ if.end:
+ ret i64 0
+}
More information about the llvm-commits
mailing list