[llvm] r276682 - AMDGPU: Remove read_workdim intrinsic
Jan Vesely via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 25 13:17:02 PDT 2016
Author: jvesely
Date: Mon Jul 25 15:17:02 2016
New Revision: 276682
URL: http://llvm.org/viewvc/llvm-project?rev=276682&view=rev
Log:
AMDGPU: Remove read_workdim intrinsic
Differential revision: https://reviews.llvm.org/D22732
Removed:
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td
llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
llvm/trunk/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td?rev=276682&r1=276681&r2=276682&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td Mon Jul 25 15:17:02 2016
@@ -41,8 +41,6 @@ defm int_r600_read_tgid : AMDGPUReadPrel
defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz;
defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz;
-def int_r600_read_workdim : AMDGPUReadPreloadRegisterIntrinsic;
-
def int_r600_group_barrier : GCCBuiltin<"__builtin_r600_group_barrier">,
Intrinsic<[], [], [IntrConvergent]>;
@@ -335,9 +333,6 @@ def int_amdgcn_buffer_atomic_cmpswap : I
llvm_i1_ty], // slc(imm)
[]>;
-def int_amdgcn_read_workdim : AMDGPUReadPreloadRegisterIntrinsic;
-
-
def int_amdgcn_buffer_wbinvl1_sc :
GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">,
Intrinsic<[], [], []>;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td?rev=276682&r1=276681&r2=276682&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUIntrinsics.td Mon Jul 25 15:17:02 2016
@@ -31,9 +31,6 @@ let TargetPrefix = "AMDGPU", isTarget =
def int_AMDGPU_rsq : Intrinsic<
[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
>;
-
- // Deprecated in favor of llvm.amdgcn.read.workdim
- def int_AMDGPU_read_workdim : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
}
include "SIIntrinsics.td"
Modified: llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=276682&r1=276681&r2=276682&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp Mon Jul 25 15:17:02 2016
@@ -747,12 +747,6 @@ SDValue R600TargetLowering::LowerOperati
case Intrinsic::r600_read_local_size_z:
return LowerImplicitParameter(DAG, VT, DL, 8);
- case Intrinsic::r600_read_workdim:
- case AMDGPUIntrinsic::AMDGPU_read_workdim: { // Legacy name.
- uint32_t ByteOffset = getImplicitParameterOffset(MFI, GRID_DIM);
- return LowerImplicitParameter(DAG, VT, DL, ByteOffset / 4);
- }
-
case Intrinsic::r600_read_tgid_x:
return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
AMDGPU::T1_X, VT);
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=276682&r1=276681&r2=276682&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Mon Jul 25 15:17:02 2016
@@ -2064,11 +2064,6 @@ SDValue SITargetLowering::LowerINTRINSIC
return lowerImplicitZextParam(DAG, Op, MVT::i16,
SI::KernelInputOffsets::LOCAL_SIZE_Z);
- case Intrinsic::amdgcn_read_workdim:
- case AMDGPUIntrinsic::AMDGPU_read_workdim: // Legacy name.
- // Really only 2 bits.
- return lowerImplicitZextParam(DAG, Op, MVT::i8,
- getImplicitParameterOffset(MFI, GRID_DIM));
case Intrinsic::amdgcn_workgroup_id_x:
case Intrinsic::r600_read_tgid_x:
return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
Modified: llvm/trunk/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll?rev=276682&r1=276681&r2=276682&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll Mon Jul 25 15:17:02 2016
@@ -4,21 +4,6 @@
; Legacy intrinsics that just read implicit parameters
-; FUNC-LABEL: {{^}}workdim_legacy:
-; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
-; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
-; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; GCN-NOHSA: buffer_store_dword [[VVAL]]
-
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
-; EG: MOV {{\*? *}}[[VAL]], KC0[2].Z
-define void @workdim_legacy (i32 addrspace(1)* %out) {
-entry:
- %0 = call i32 @llvm.AMDGPU.read.workdim() #0
- store i32 %0, i32 addrspace(1)* %out
- ret void
-}
-
; FUNC-LABEL: {{^}}ngroups_x:
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
@@ -263,6 +248,4 @@ declare i32 @llvm.r600.read.tidig.x() #0
declare i32 @llvm.r600.read.tidig.y() #0
declare i32 @llvm.r600.read.tidig.z() #0
-declare i32 @llvm.AMDGPU.read.workdim() #0
-
attributes #0 = { readnone }
Removed: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll?rev=276681&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll (removed)
@@ -1,46 +0,0 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA %s
-
-; GCN-LABEL: {{^}}read_workdim:
-; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
-; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
-; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; GCN-NOHSA: buffer_store_dword [[VVAL]]
-define void @read_workdim(i32 addrspace(1)* %out) {
-entry:
- %0 = call i32 @llvm.amdgcn.read.workdim() #0
- store i32 %0, i32 addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}read_workdim_known_bits:
-; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
-; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
-; GCN-NOT: 0xff
-; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; GCN: buffer_store_dword [[VVAL]]
-define void @read_workdim_known_bits(i32 addrspace(1)* %out) {
-entry:
- %dim = call i32 @llvm.amdgcn.read.workdim() #0
- %shl = shl i32 %dim, 24
- %shr = lshr i32 %shl, 24
- store i32 %shr, i32 addrspace(1)* %out
- ret void
-}
-
-; GCN-LABEL: {{^}}legacy_read_workdim:
-; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
-; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
-; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
-; GCN-NOHSA: buffer_store_dword [[VVAL]]
-define void @legacy_read_workdim(i32 addrspace(1)* %out) {
-entry:
- %dim = call i32 @llvm.AMDGPU.read.workdim() #0
- store i32 %dim, i32 addrspace(1)* %out
- ret void
-}
-
-declare i32 @llvm.amdgcn.read.workdim() #0
-declare i32 @llvm.AMDGPU.read.workdim() #0
-
-attributes #0 = { nounwind readnone }
Removed: llvm/trunk/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll?rev=276681&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll (removed)
@@ -1,36 +0,0 @@
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
-
-; EG-LABEL: {{^}}read_workdim:
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
-; EG: MOV * [[VAL]], KC0[2].Z
-define void @read_workdim(i32 addrspace(1)* %out) {
-entry:
- %dim = call i32 @llvm.r600.read.workdim() #0
- store i32 %dim, i32 addrspace(1)* %out
- ret void
-}
-
-; EG-LABEL: {{^}}read_workdim_known_bits:
-define void @read_workdim_known_bits(i32 addrspace(1)* %out) {
-entry:
- %dim = call i32 @llvm.r600.read.workdim() #0
- %shl = shl i32 %dim, 24
- %shr = lshr i32 %shl, 24
- store i32 %shr, i32 addrspace(1)* %out
- ret void
-}
-
-; EG-LABEL: {{^}}legacy_read_workdim:
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
-; EG: MOV * [[VAL]], KC0[2].Z
-define void @legacy_read_workdim(i32 addrspace(1)* %out) {
-entry:
- %dim = call i32 @llvm.AMDGPU.read.workdim() #0
- store i32 %dim, i32 addrspace(1)* %out
- ret void
-}
-
-declare i32 @llvm.r600.read.workdim() #0
-declare i32 @llvm.AMDGPU.read.workdim() #0
-
-attributes #0 = { nounwind readnone }
Modified: llvm/trunk/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll?rev=276682&r1=276681&r2=276682&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll Mon Jul 25 15:17:02 2016
@@ -78,22 +78,6 @@ define void @test_implicit_dyn(i32 addrs
ret void
}
-
-
-; DEPRECATED but R600 only
-
-; FUNC-LABEL: {{^}}workdim:
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
-; EG: MOV {{\*? *}}[[VAL]], KC0[2].Z
-define void @workdim (i32 addrspace(1)* %out) {
-entry:
- %0 = call i32 @llvm.r600.read.workdim() #0
- store i32 %0, i32 addrspace(1)* %out
- ret void
-}
-
-declare i32 @llvm.r600.read.workdim() #0
-
declare i8 addrspace(7)* @llvm.r600.implicitarg.ptr() #0
declare i32 @llvm.r600.read.tgid.x() #0
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