[llvm] r276675 - AMDGPU: Delete dead code
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 25 12:06:26 PDT 2016
Author: arsenm
Date: Mon Jul 25 14:06:25 2016
New Revision: 276675
URL: http://llvm.org/viewvc/llvm-project?rev=276675&view=rev
Log:
AMDGPU: Delete dead code
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=276675&r1=276674&r2=276675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Mon Jul 25 14:06:25 2016
@@ -55,14 +55,6 @@ EVT AMDGPUTargetLowering::getEquivalentM
return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
}
-EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) {
- unsigned StoreSize = VT.getStoreSizeInBits();
- if (StoreSize <= 32)
- return EVT::getIntegerVT(Ctx, StoreSize);
-
- return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
-}
-
AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
const AMDGPUSubtarget &STI)
: TargetLowering(TM), Subtarget(&STI) {
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h?rev=276675&r1=276674&r2=276675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h Mon Jul 25 14:06:25 2016
@@ -75,7 +75,6 @@ protected:
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
- static EVT getEquivalentBitType(LLVMContext &Context, EVT VT);
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
SelectionDAG &DAG) const;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=276675&r1=276674&r2=276675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Mon Jul 25 14:06:25 2016
@@ -193,19 +193,6 @@ SISubtarget::SISubtarget(const Triple &T
TLInfo(TM, *this),
GISel() {}
-unsigned R600Subtarget::getStackEntrySize() const {
- switch (getWavefrontSize()) {
- case 16:
- return 8;
- case 32:
- return hasCaymanISA() ? 4 : 8;
- case 64:
- return 4;
- default:
- llvm_unreachable("Illegal wavefront size.");
- }
-}
-
void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
unsigned NumRegionInstrs) const {
// Track register pressure so the scheduler can try to decrease
@@ -226,16 +213,3 @@ void SISubtarget::overrideSchedPolicy(Ma
bool SISubtarget::isVGPRSpillingEnabled(const Function& F) const {
return EnableVGPRSpilling || !AMDGPU::isShader(F.getCallingConv());
}
-
-unsigned SISubtarget::getAmdKernelCodeChipID() const {
- switch (getGeneration()) {
- case SEA_ISLANDS:
- return 12;
- default:
- llvm_unreachable("ChipID unknown");
- }
-}
-
-AMDGPU::IsaVersion SISubtarget::getIsaVersion() const {
- return AMDGPU::getIsaVersion(getFeatureBits());
-}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=276675&r1=276674&r2=276675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Mon Jul 25 14:06:25 2016
@@ -328,8 +328,6 @@ public:
short getTexVTXClauseSize() const {
return TexVTXClauseSize;
}
-
- unsigned getStackEntrySize() const;
};
class SISubtarget final : public AMDGPUSubtarget {
@@ -378,10 +376,6 @@ public:
bool isVGPRSpillingEnabled(const Function& F) const;
- unsigned getAmdKernelCodeChipID() const;
-
- AMDGPU::IsaVersion getIsaVersion() const;
-
unsigned getMaxNumUserSGPRs() const {
return 16;
}
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