[PATCH] D22726: [DAGCombine] Match shift amount by value rather than relying on common sub-expressions.

[Eli Friedman via llvm-commits]

eli.friedman added inline comments.

================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4832
@@ +4831,3 @@
+      isa<ConstantSDNode>(N0.getOperand(1)) &&
+      cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue().getBitWidth() <=
+          64 &&
----------------
There's some code near the beginning of the function which makes sure N1C is less than the bitwidth of the LHS.  (LLVM only supports integers with sizes up to 2^24 bits or so.)  Granted, it looks like it also uses getZExtValue incorrectly, so the following crashes:

```
define <2 x i128> @y(<2 x i128>* byval align 32) #0 {
entry:
  %a.addr = alloca <2 x i128>, align 32
  %a = load <2 x i128>, <2 x i128>* %0, align 32
  store <2 x i128> %a, <2 x i128>* %a.addr, align 32
  %1 = load <2 x i128>, <2 x i128>* %a.addr, align 32
  %shr = lshr <2 x i128> %1, <i128 -1, i128 -1>
  ret <2 x i128> %shr
}
```

Patch welcome. :)


Repository:
  rL LLVM

https://reviews.llvm.org/D22726