[PATCH] D22726: [DAGCombine] Match shift amount by value rather than relying on common sub-expressions.

[bryant via llvm-commits]

bryant added inline comments.

================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:4832
@@ +4831,3 @@
+      isa<ConstantSDNode>(N0.getOperand(1)) &&
+      cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue() ==
+          N1C->getZExtValue()) {
----------------
eli.friedman wrote:
> You can't use getZExtValue on an arbitrary constant; it will crash if the constant is too large.
Thanks. APInt indeed asserts that the bit width occupied by the value fits within a `uint64_t`.

Bbut doesn't the code two lines below (and in the rest of this function) make the same assumption about constant nodes, albeit about `N1C`?


Repository:
  rL LLVM

https://reviews.llvm.org/D22726