[llvm] r276569 - [X86] Add 'FeatureSlowSHLD' to cpu 'bdver4'

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Jul 24 11:00:53 2016
New Revision: 276569

URL: http://llvm.org/viewvc/llvm-project?rev=276569&view=rev
Log:
[X86] Add 'FeatureSlowSHLD' to cpu 'bdver4'

As with all AMD CPUs, excavator has poor SHLD/SHRD performance. Also added bdver3 to the test as it was missing.


Modified:
    llvm/trunk/lib/Target/X86/X86.td
    llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll

Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=276569&r1=276568&r2=276569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Sun Jul 24 11:00:53 2016
@@ -729,6 +729,7 @@ def : Proc<"bdver4", [
   FeatureTBM,
   FeatureFMA,
   FeatureXSAVEOPT,
+  FeatureSlowSHLD,
   FeatureFSGSBase,
   FeatureLAHFSAHF,
   FeatureMWAITX

Modified: llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll?rev=276569&r1=276568&r2=276569&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-double-shifts-var.ll Sun Jul 24 11:00:53 2016
@@ -15,6 +15,8 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=btver2 | FileCheck %s
 ; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
 ; RUN: llc < %s -march=x86-64 -mcpu=bdver2 | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mcpu=bdver3 | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mcpu=bdver4 | FileCheck %s
 
 ; Verify that for the X86_64 processors that are known to have poor latency 
 ; double precision shift instructions we do not generate 'shld' or 'shrd'