[llvm] r276567 - [X86] Regenerate shift by parts tests

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Jul 24 10:38:51 2016
New Revision: 276567

URL: http://llvm.org/viewvc/llvm-project?rev=276567&view=rev
Log:
[X86] Regenerate shift by parts tests


Modified:
    llvm/trunk/test/CodeGen/X86/shift-double.ll

Modified: llvm/trunk/test/CodeGen/X86/shift-double.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-double.ll?rev=276567&r1=276566&r2=276567&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-double.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-double.ll Sun Jul 24 10:38:51 2016
@@ -1,25 +1,88 @@
-; RUN: llc < %s -march=x86 -mcpu=generic -x86-asm-syntax=intel | \
-; RUN:   grep "sh[lr]d" | count 5
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s
 
-define i64 @test1(i64 %X, i8 %C) {
+; Shift i64 integers on 32-bit target
+
+define i64 @test1(i64 %X, i8 %C) nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    shldl %cl, %esi, %edx
+; CHECK-NEXT:    testb $32, %cl
+; CHECK-NEXT:    je .LBB0_2
+; CHECK-NEXT:  # BB#1:
+; CHECK-NEXT:    movl %eax, %edx
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
         %shift.upgrd.1 = zext i8 %C to i64              ; <i64> [#uses=1]
         %Y = shl i64 %X, %shift.upgrd.1         ; <i64> [#uses=1]
         ret i64 %Y
 }
 
-define i64 @test2(i64 %X, i8 %C) {
+define i64 @test2(i64 %X, i8 %C) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl %esi, %edx
+; CHECK-NEXT:    sarl %cl, %edx
+; CHECK-NEXT:    shrdl %cl, %esi, %eax
+; CHECK-NEXT:    testb $32, %cl
+; CHECK-NEXT:    je .LBB1_2
+; CHECK-NEXT:  # BB#1:
+; CHECK-NEXT:    sarl $31, %esi
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    movl %esi, %edx
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
         %shift.upgrd.2 = zext i8 %C to i64              ; <i64> [#uses=1]
         %Y = ashr i64 %X, %shift.upgrd.2                ; <i64> [#uses=1]
         ret i64 %Y
 }
 
-define i64 @test3(i64 %X, i8 %C) {
+define i64 @test3(i64 %X, i8 %C) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl %esi, %edx
+; CHECK-NEXT:    shrl %cl, %edx
+; CHECK-NEXT:    shrdl %cl, %esi, %eax
+; CHECK-NEXT:    testb $32, %cl
+; CHECK-NEXT:    je .LBB2_2
+; CHECK-NEXT:  # BB#1:
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:  .LBB2_2:
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
         %shift.upgrd.3 = zext i8 %C to i64              ; <i64> [#uses=1]
         %Y = lshr i64 %X, %shift.upgrd.3                ; <i64> [#uses=1]
         ret i64 %Y
 }
 
-define i32 @test4(i32 %A, i32 %B, i8 %C) {
+; Combine 2xi32/2xi16 shifts into SHLD
+
+define i32 @test4(i32 %A, i32 %B, i8 %C) nounwind {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    shldl %cl, %edx, %eax
+; CHECK-NEXT:    retl
         %shift.upgrd.4 = zext i8 %C to i32              ; <i32> [#uses=1]
         %X = shl i32 %A, %shift.upgrd.4         ; <i32> [#uses=1]
         %Cv = sub i8 32, %C             ; <i8> [#uses=1]
@@ -29,7 +92,14 @@ define i32 @test4(i32 %A, i32 %B, i8 %C)
         ret i32 %Z
 }
 
-define i16 @test5(i16 %A, i16 %B, i8 %C) {
+define i16 @test5(i16 %A, i16 %B, i8 %C) nounwind {
+; CHECK-LABEL: test5:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    shldw %cl, %dx, %ax
+; CHECK-NEXT:    retl
         %shift.upgrd.6 = zext i8 %C to i16              ; <i16> [#uses=1]
         %X = shl i16 %A, %shift.upgrd.6         ; <i16> [#uses=1]
         %Cv = sub i8 16, %C             ; <i8> [#uses=1]