[llvm] r276526 - [X86][SSE] Regenerated uitofp <2 x i32> -> <2 x float> conversion tests

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Jul 23 10:55:42 2016
New Revision: 276526

URL: http://llvm.org/viewvc/llvm-project?rev=276526&view=rev
Log:
[X86][SSE] Regenerated uitofp <2 x i32> -> <2 x float> conversion tests

Demonstrate difference in codegen discussed on PR14760

Modified:
    llvm/trunk/test/CodeGen/X86/cvtv2f32.ll

Modified: llvm/trunk/test/CodeGen/X86/cvtv2f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cvtv2f32.ll?rev=276526&r1=276525&r2=276526&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cvtv2f32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cvtv2f32.ll Sat Jul 23 10:55:42 2016
@@ -1,29 +1,64 @@
-; A bug fix in the DAGCombiner made this test fail, so marking as xfail
-; until this can be investigated further.
-; XFAIL: *
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X64
 
-; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s
+; FIXME: As discussed on PR14760, we currently have a difference in uitofp <2 x i32> codegen between
+; buildvector and legalization on 32-bit targets:
 
-define <2 x float> @foo(i32 %x, i32 %y, <2 x float> %v) {
+define <2 x float> @uitofp_2i32_buildvector(i32 %x, i32 %y, <2 x float> %v) {
+; X32-LABEL: uitofp_2i32_buildvector:
+; X32:       # BB#0:
+; X32-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
+; X32-NEXT:    movdqa {{.*#+}} xmm2 = [1258291200,1258291200,1258291200,1258291200]
+; X32-NEXT:    pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
+; X32-NEXT:    psrld $16, %xmm1
+; X32-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0],mem[1],xmm1[2],mem[3],xmm1[4],mem[5],xmm1[6],mem[7]
+; X32-NEXT:    addps {{\.LCPI.*}}, %xmm1
+; X32-NEXT:    addps %xmm2, %xmm1
+; X32-NEXT:    mulps %xmm1, %xmm0
+; X32-NEXT:    retl
+;
+; X64-LABEL: uitofp_2i32_buildvector:
+; X64:       # BB#0:
+; X64-NEXT:    movd %edi, %xmm1
+; X64-NEXT:    pinsrd $1, %esi, %xmm1
+; X64-NEXT:    movdqa {{.*#+}} xmm2 = [1258291200,1258291200,1258291200,1258291200]
+; X64-NEXT:    pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
+; X64-NEXT:    psrld $16, %xmm1
+; X64-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0],mem[1],xmm1[2],mem[3],xmm1[4],mem[5],xmm1[6],mem[7]
+; X64-NEXT:    addps {{.*}}(%rip), %xmm1
+; X64-NEXT:    addps %xmm2, %xmm1
+; X64-NEXT:    mulps %xmm1, %xmm0
+; X64-NEXT:    retq
   %t1 = uitofp i32 %x to float
   %t2 = insertelement <2 x float> undef, float %t1, i32 0
   %t3 = uitofp i32 %y to float
   %t4 = insertelement <2 x float> %t2, float %t3, i32 1
   %t5 = fmul <2 x float> %v, %t4
   ret <2 x float> %t5
-; CHECK: foo
-; CHECK: or
-; CHECK: subpd
-; CHECK: cvtpd2ps
-; CHECK: ret
 }
 
-define <2 x float> @bar(<2 x i32> %in) {
+define <2 x float> @uitofp_2i32_legalized(<2 x i32> %in) {
+; X32-LABEL: uitofp_2i32_legalized:
+; X32:       # BB#0:
+; X32-NEXT:    pxor %xmm1, %xmm1
+; X32-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X32-NEXT:    movdqa {{.*#+}} xmm0 = [4.503600e+15,4.503600e+15]
+; X32-NEXT:    por %xmm0, %xmm1
+; X32-NEXT:    subpd %xmm0, %xmm1
+; X32-NEXT:    cvtpd2ps %xmm1, %xmm0
+; X32-NEXT:    retl
+;
+; X64-LABEL: uitofp_2i32_legalized:
+; X64:       # BB#0:
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X64-NEXT:    movdqa {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200]
+; X64-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; X64-NEXT:    psrld $16, %xmm0
+; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
+; X64-NEXT:    addps {{.*}}(%rip), %xmm0
+; X64-NEXT:    addps %xmm1, %xmm0
+; X64-NEXT:    retq
   %r = uitofp <2 x i32> %in to <2 x float>
   ret <2 x float> %r
-; CHECK: bar
-; CHECK: or
-; CHECK: subpd
-; CHECK: cvtpd2ps
-; CHECK: ret
 }