[PATCH] D22667: [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
This revision now requires changes to proceed.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:651-663
@@ -640,12 +650,15 @@
                                        Rs)));
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
   } else if (Rs != 0 && Rs < Rt) {
     MI.setOpcode(Mips::BEQC_MMR6);
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rs)));
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rt)));
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
   } else {
     MI.setOpcode(Mips::BEQZALC_MMR6);
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rt)));
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
   }
----------------
The current '* 2"s should be changed to '* 2 + 4'.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:724-736
@@ -710,11 +723,15 @@
                                        Rs)));
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
   } else if (Rs != 0 && Rs < Rt) {
     MI.setOpcode(Mips::BNEC_MMR6);
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rs)));
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rt)));
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
   } else {
     MI.setOpcode(Mips::BNEZALC_MMR6);
     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
                                        Rt)));
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
+  }
----------------
Here too.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:755
@@ +754,3 @@
+
+  bool HasRs = false;
+
----------------
Style point, you can put this line after the 'int64_t Imm..' line like the next function for consistency.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:2392-2403
@@ -2296,11 +2391,14 @@
     HasRt = true;
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
   }
   else if (Rs == Rt) {
     MI.setOpcode(Mips::BLTZALC_MMR6);
     HasRs = true;
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
   }
   else {
     MI.setOpcode(Mips::BLTUC_MMR6);
     HasRs = true;
     HasRt = true;
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
   }
----------------
Here again '* 2' -> '* 2 + 4'.

================
Comment at: lib/Target/Mips/Disassembler/MipsDisassembler.cpp:2437-2448
@@ -2338,9 +2436,14 @@
     return MCDisassembler::Fail;
-  else if (Rs == 0)
+  else if (Rs == 0) {
     MI.setOpcode(Mips::BLEZALC_MMR6);
-  else if (Rs == Rt)
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
+  }
+  else if (Rs == Rt) {
     MI.setOpcode(Mips::BGEZALC_MMR6);
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2;
+  }
   else {
     HasRs = true;
     MI.setOpcode(Mips::BGEUC_MMR6);
+    Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
   }
----------------
Here again.

================
Comment at: test/MC/Mips/micromips32r6/invalid.s:301
@@ +300,2 @@
+  beqzc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
+  bnezc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
----------------
Add out of range tests as well,  and unencodable offsets and to the other invalid test.


https://reviews.llvm.org/D22667