[llvm] r276422 - [Hexagon] Use loop data prefetch on Hexagon

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Jul 22 09:22:43 2016
New Revision: 276422

URL: http://llvm.org/viewvc/llvm-project?rev=276422&view=rev
Log:
[Hexagon] Use loop data prefetch on Hexagon

Added:
    llvm/trunk/test/CodeGen/Hexagon/loop-prefetch.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
    llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h

Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=276422&r1=276421&r2=276422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Fri Jul 22 09:22:43 2016
@@ -367,3 +367,11 @@ void HexagonSubtarget::adjustSchedDepend
   updateLatency(SrcInst, DstInst, Dep);
 }
 
+unsigned HexagonSubtarget::getL1CacheLineSize() const {
+  return 32;
+}
+
+unsigned HexagonSubtarget::getL1PrefetchDistance() const {
+  return 32;
+}
+

Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=276422&r1=276421&r2=276422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Fri Jul 22 09:22:43 2016
@@ -132,6 +132,9 @@ public:
   /// dependency.
   void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
 
+  unsigned getL1CacheLineSize() const;
+  unsigned getL1PrefetchDistance() const;
+
 private:
   // Helper function responsible for increasing the latency only.
   void updateLatency(MachineInstr *SrcInst, MachineInstr *DstInst, SDep &Dep)

Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=276422&r1=276421&r2=276422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp Fri Jul 22 09:22:43 2016
@@ -68,6 +68,10 @@ static cl::opt<bool> EnableGenPred("hexa
   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
   "predicate instructions"));
 
+static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
+  cl::init(false), cl::Hidden, cl::ZeroOrMore,
+  cl::desc("Enable loop data prefetch on Hexagon"));
+
 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
   cl::desc("Disable splitting double registers"));
 
@@ -225,6 +229,8 @@ void HexagonPassConfig::addIRPasses() {
 
   addPass(createAtomicExpandPass(TM));
   if (!NoOpt) {
+    if (EnableLoopPrefetch)
+      addPass(createLoopDataPrefetchPass());
     if (EnableCommGEP)
       addPass(createHexagonCommonGEP());
     // Replace certain combinations of shifts and ands with extracts.

Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp?rev=276422&r1=276421&r2=276422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp Fri Jul 22 09:22:43 2016
@@ -36,3 +36,11 @@ void HexagonTTIImpl::getUnrollingPrefere
 unsigned HexagonTTIImpl::getNumberOfRegisters(bool vector) const {
   return vector ? 0 : 32;
 }
+
+unsigned HexagonTTIImpl::getPrefetchDistance() const {
+  return getST()->getL1PrefetchDistance();
+}
+
+unsigned HexagonTTIImpl::getCacheLineSize() const {
+  return getST()->getL1CacheLineSize();
+}

Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h?rev=276422&r1=276421&r2=276422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h Fri Jul 22 09:22:43 2016
@@ -55,6 +55,10 @@ public:
   // The Hexagon target can unroll loops with run-time trip counts.
   void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
 
+  // L1 cache prefetch.
+  unsigned getPrefetchDistance() const;
+  unsigned getCacheLineSize() const;
+
   /// @}
 
   /// \name Vector TTI Implementations

Added: llvm/trunk/test/CodeGen/Hexagon/loop-prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/loop-prefetch.ll?rev=276422&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/loop-prefetch.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/loop-prefetch.ll Fri Jul 22 09:22:43 2016
@@ -0,0 +1,27 @@
+; RUN: llc -march=hexagon -hexagon-loop-prefetch < %s | FileCheck %s
+; CHECK: dcfetch
+
+target triple = "hexagon"
+
+define void @copy(i32* nocapture %d, i32* nocapture readonly %s, i32 %n) local_unnamed_addr #0 {
+entry:
+  %tobool2 = icmp eq i32 %n, 0
+  br i1 %tobool2, label %while.end, label %while.body
+
+while.body:                                       ; preds = %entry, %while.body
+  %n.addr.05 = phi i32 [ %dec, %while.body ], [ %n, %entry ]
+  %s.addr.04 = phi i32* [ %incdec.ptr, %while.body ], [ %s, %entry ]
+  %d.addr.03 = phi i32* [ %incdec.ptr1, %while.body ], [ %d, %entry ]
+  %dec = add i32 %n.addr.05, -1
+  %incdec.ptr = getelementptr inbounds i32, i32* %s.addr.04, i32 1
+  %0 = load i32, i32* %s.addr.04, align 4
+  %incdec.ptr1 = getelementptr inbounds i32, i32* %d.addr.03, i32 1
+  store i32 %0, i32* %d.addr.03, align 4
+  %tobool = icmp eq i32 %dec, 0
+  br i1 %tobool, label %while.end, label %while.body
+
+while.end:                                        ; preds = %while.body, %entry
+  ret void
+}
+
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" }