[llvm] r276397 - [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
Hrvoje Varga via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 22 00:18:34 PDT 2016
Author: hvarga
Date: Fri Jul 22 02:18:33 2016
New Revision: 276397
URL: http://llvm.org/viewvc/llvm-project?rev=276397&view=rev
Log:
[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
Differential Revision: https://reviews.llvm.org/D19906
Added:
llvm/trunk/test/CodeGen/Mips/slt.ll
Modified:
llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/trunk/test/CodeGen/Mips/brconlt.ll
llvm/trunk/test/CodeGen/Mips/setcc-se.ll
llvm/trunk/test/CodeGen/Mips/seteq.ll
llvm/trunk/test/CodeGen/Mips/seteqz.ll
llvm/trunk/test/CodeGen/Mips/setge.ll
llvm/trunk/test/CodeGen/Mips/setgek.ll
llvm/trunk/test/CodeGen/Mips/setle.ll
llvm/trunk/test/CodeGen/Mips/setlt.ll
llvm/trunk/test/CodeGen/Mips/setltk.ll
llvm/trunk/test/CodeGen/Mips/setne.ll
llvm/trunk/test/CodeGen/Mips/setuge.ll
llvm/trunk/test/CodeGen/Mips/setugt.ll
llvm/trunk/test/CodeGen/Mips/setule.ll
llvm/trunk/test/CodeGen/Mips/setult.ll
llvm/trunk/test/CodeGen/Mips/setultk.ll
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Mips/micromips-el-fixup-data.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp Fri Jul 22 02:18:33 2016
@@ -236,6 +236,7 @@ bool MipsInstPrinter::printAlias(const M
// beq $r0, $zero, $L2 => beqz $r0, $L2
return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
case Mips::BNE:
+ case Mips::BNE_MM:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
case Mips::BNE64:
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Fri Jul 22 02:18:33 2016
@@ -1047,6 +1047,15 @@ def : MipsPat<(atomic_load_16 addr:$a),
def : MipsPat<(i32 (extloadi16 addr:$src)),
(LHu_MM addr:$src)>;
+defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
+ SLTiu_MM, ZERO>;
+
+defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
+defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
+defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
+defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
+defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>;
+
//===----------------------------------------------------------------------===//
// MicroMips instruction aliases
//===----------------------------------------------------------------------===//
@@ -1080,6 +1089,12 @@ let Predicates = [InMicroMips] in {
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+ def : MipsInstAlias<"slt $rs, $rt, $imm",
+ (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
+ simm32_relaxed:$imm), 0>;
+ def : MipsInstAlias<"sltu $rs, $rt, $imm",
+ (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
+ simm32_relaxed:$imm), 0>;
def : MipsInstAlias<"sll $rd, $rt, $rs",
(SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
def : MipsInstAlias<"sra $rd, $rt, $rs",
@@ -1115,4 +1130,8 @@ let Predicates = [InMicroMips] in {
(XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
def : MipsInstAlias<"not $rt, $rs",
(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
+ def : MipsInstAlias<"bnez $rs,$offset",
+ (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
+ def : MipsInstAlias<"beqz $rs,$offset",
+ (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
}
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Fri Jul 22 02:18:33 2016
@@ -537,21 +537,21 @@ let AdditionalPredicates = [NotInMicroMi
def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
}
-defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
+defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
ZERO_64>;
-
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
(BLEZ64 i64:$lhs, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
(BGEZ64 i64:$lhs, bb:$dst)>;
// setcc patterns
-defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
-defm : SetlePats<GPR64, SLT64, SLTu64>;
-defm : SetgtPats<GPR64, SLT64, SLTu64>;
-defm : SetgePats<GPR64, SLT64, SLTu64>;
-defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
-
+let AdditionalPredicates = [NotInMicroMips] in {
+ defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
+ defm : SetlePats<GPR64, XORi, SLT64, SLTu64>;
+ defm : SetgtPats<GPR64, SLT64, SLTu64>;
+ defm : SetgePats<GPR64, XORi, SLT64, SLTu64>;
+ defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>;
+}
// truncate
def : MipsPat<(trunc (assertsext GPR64:$src)),
(EXTRACT_SUBREG GPR64:$src, sub_32)>;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Jul 22 02:18:33 2016
@@ -269,7 +269,9 @@ unsigned MipsInstrInfo::getEquivalentCom
if (Subtarget.inMicroMipsMode()) {
switch (Opcode) {
case Mips::BNE:
+ case Mips::BNE_MM:
case Mips::BEQ:
+ case Mips::BEQ_MM:
// microMIPS has NE,EQ branches that do not have delay slots provided one
// of the operands is zero.
if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
@@ -302,12 +304,14 @@ unsigned MipsInstrInfo::getEquivalentCom
case Mips::BAL:
return Mips::BALC;
case Mips::BEQ:
+ case Mips::BEQ_MM:
if (canUseShortMicroMipsCTI)
return Mips::BEQZC_MM;
else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
return 0;
return Mips::BEQC;
case Mips::BNE:
+ case Mips::BNE_MM:
if (canUseShortMicroMipsCTI)
return Mips::BNEZC_MM;
else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Jul 22 02:18:33 2016
@@ -1686,33 +1686,35 @@ let AdditionalPredicates = [NotInMicroMi
}
def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>,
ISA_MIPS1_NOT_32R6_64R6;
-def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
- SLTI_FM<0xa>;
-def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
- SLTI_FM<0xb>;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
+ SLTI_FM<0xa>;
+ def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
+ SLTI_FM<0xb>;
+}
def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
let AdditionalPredicates = [NotInMicroMips] in {
-/// Arithmetic Instructions (3-Operand, R-Type)
-def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
- ADD_FM<0, 0x21>;
-def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
- ADD_FM<0, 0x23>;
+ /// Arithmetic Instructions (3-Operand, R-Type)
+ def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
+ ADD_FM<0, 0x21>;
+ def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
+ ADD_FM<0, 0x23>;
}
let Defs = [HI0, LO0] in
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>;
def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>;
-def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
-def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
let AdditionalPredicates = [NotInMicroMips] in {
-def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
- ADD_FM<0, 0x24>;
-def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
- ADD_FM<0, 0x25>;
-def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
- ADD_FM<0, 0x26>;
-def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
+ def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
+ def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
+ def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
+ ADD_FM<0, 0x24>;
+ def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
+ ADD_FM<0, 0x25>;
+ def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
+ ADD_FM<0, 0x26>;
+ def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
}
/// Shift Instructions
@@ -2223,13 +2225,13 @@ def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"negu $rt, $rs",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
-def : MipsInstAlias<
+let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<
"slt $rs, $rt, $imm",
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
-def : MipsInstAlias<
+ def : MipsInstAlias<
"sltu $rt, $rs, $imm",
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
-let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<
"and $rs, $rt, $imm",
(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
@@ -2558,38 +2560,39 @@ let AdditionalPredicates = [NotInMicroMi
def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
// brcond patterns
-multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
- Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
- Instruction SLTiuOp, Register ZEROReg> {
+multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1,
+ Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp,
+ Instruction SLTiOp, Instruction SLTiuOp,
+ Register ZEROReg> {
def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
(BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
(BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
- (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
- (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
- (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
- (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
- (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
+ (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
def : MipsPat<(brcond RC:$cond, bb:$dst),
(BNEOp RC:$cond, ZEROReg, bb:$dst)>;
}
-
-defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
-
+let AdditionalPredicates = [NotInMicroMips] in {
+ defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
+}
def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
(BLEZ i32:$lhs, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
@@ -2608,11 +2611,12 @@ multiclass SeteqPats<RegisterClass RC, I
(SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
}
-multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
+multiclass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,
+ Instruction SLTuOp> {
def : MipsPat<(setle RC:$lhs, RC:$rhs),
- (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
+ (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>;
def : MipsPat<(setule RC:$lhs, RC:$rhs),
- (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
+ (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>;
}
multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
@@ -2622,26 +2626,29 @@ multiclass SetgtPats<RegisterClass RC, I
(SLTuOp RC:$rhs, RC:$lhs)>;
}
-multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
+multiclass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,
+ Instruction SLTuOp> {
def : MipsPat<(setge RC:$lhs, RC:$rhs),
- (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
+ (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>;
def : MipsPat<(setuge RC:$lhs, RC:$rhs),
- (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
+ (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>;
}
-multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
- Instruction SLTiuOp> {
+multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp,
+ Instruction SLTiOp, Instruction SLTiuOp> {
def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
- (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
+ (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
- (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
+ (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
}
-defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
-defm : SetlePats<GPR32, SLT, SLTu>;
-defm : SetgtPats<GPR32, SLT, SLTu>;
-defm : SetgePats<GPR32, SLT, SLTu>;
-defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
+let AdditionalPredicates = [NotInMicroMips] in {
+ defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
+ defm : SetlePats<GPR32, XORi, SLT, SLTu>;
+ defm : SetgtPats<GPR32, SLT, SLTu>;
+ defm : SetgePats<GPR32, XORi, SLT, SLTu>;
+ defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>;
+}
// bswap pattern
def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
Modified: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp Fri Jul 22 02:18:33 2016
@@ -408,7 +408,9 @@ unsigned MipsSEInstrInfo::getOppositeBra
switch (Opc) {
default: llvm_unreachable("Illegal opcode!");
case Mips::BEQ: return Mips::BNE;
+ case Mips::BEQ_MM: return Mips::BNE_MM;
case Mips::BNE: return Mips::BEQ;
+ case Mips::BNE_MM: return Mips::BEQ_MM;
case Mips::BGTZ: return Mips::BLEZ;
case Mips::BGEZ: return Mips::BLTZ;
case Mips::BLTZ: return Mips::BGEZ;
@@ -506,16 +508,17 @@ unsigned MipsSEInstrInfo::loadImmediate(
}
unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
- return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
- Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
- Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
- Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
- Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
- Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM ||
- Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC ||
- Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC ||
- Opc == Mips::BGTZC || Opc == Mips::BLEZC || Opc == Mips::BGEZC ||
- Opc == Mips::BLTZC || Opc == Mips::BEQZC || Opc == Mips::BNEZC ||
+ return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
+ Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
+ Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
+ Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
+ Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
+ Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
+ Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
+ Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
+ Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
+ Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
+ Opc == Mips::BEQZC || Opc == Mips::BNEZC ||
Opc == Mips::BC) ? Opc : 0;
}
Modified: llvm/trunk/test/CodeGen/Mips/brconlt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/brconlt.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/brconlt.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/brconlt.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
@i = global i32 5, align 4
@j = global i32 10, align 4
@@ -12,9 +13,10 @@ entry:
%cmp = icmp slt i32 %0, %1
br i1 %cmp, label %if.end, label %if.then
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
-; 16: $[[LABEL]]:
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}}
+; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
+; 16: $[[LABEL]]:
if.then: ; preds = %entry
store i32 1, i32* @result, align 4
Modified: llvm/trunk/test/CodeGen/Mips/setcc-se.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setcc-se.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setcc-se.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setcc-se.ll Fri Jul 22 02:18:33 2016
@@ -1,9 +1,12 @@
; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
@g1 = external global i32
; CHECK-LABEL: seteq0:
-; CHECK: sltiu ${{[0-9]+}}, $4, 1
+; CHECK: sltiu ${{[0-9]+}}, $4, 1
+; MMR6: sltiu ${{[0-9]+}}, $4, 1
+; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
define i32 @seteq0(i32 %a) {
entry:
@@ -13,7 +16,9 @@ entry:
}
; CHECK-LABEL: setne0:
-; CHECK: sltu ${{[0-9]+}}, $zero, $4
+; CHECK: sltu ${{[0-9]+}}, $zero, $4
+; MMR6: sltu ${{[0-9]+}}, $zero, $4
+; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
define i32 @setne0(i32 %a) {
entry:
@@ -23,8 +28,10 @@ entry:
}
; CHECK-LABEL: slti_beq0:
-; CHECK: slti $[[R0:[0-9]+]], $4, -32768
-; CHECK: beqz $[[R0]]
+; CHECK: slti $[[R0:[0-9]+]], $4, -32768
+; MMR6: slti $[[R0:[0-9]+]], $4, -32768
+; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
+; CHECK: beqz $[[R0]]
define void @slti_beq0(i32 %a) {
entry:
@@ -40,7 +47,9 @@ if.end:
}
; CHECK-LABEL: slti_beq1:
-; CHECK: slt ${{[0-9]+}}
+; CHECK: slt ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLT_MM
define void @slti_beq1(i32 %a) {
entry:
@@ -56,8 +65,10 @@ if.end:
}
; CHECK-LABEL: slti_beq2:
-; CHECK: slti $[[R0:[0-9]+]], $4, 32767
-; CHECK: beqz $[[R0]]
+; CHECK: slti $[[R0:[0-9]+]], $4, 32767
+; MMR6: slti $[[R0:[0-9]+]], $4, 32767
+; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
+; CHECK: beqz $[[R0]]
define void @slti_beq2(i32 %a) {
entry:
@@ -73,7 +84,9 @@ if.end:
}
; CHECK-LABEL: slti_beq3:
-; CHECK: slt ${{[0-9]+}}
+; CHECK: slt ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLT_MM
define void @slti_beq3(i32 %a) {
entry:
@@ -89,8 +102,10 @@ if.end:
}
; CHECK-LABEL: sltiu_beq0:
-; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
-; CHECK: beqz $[[R0]]
+; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
+; MMR6: sltiu $[[R0:[0-9]+]], $4, 32767
+; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
+; CHECK: beqz $[[R0]]
define void @sltiu_beq0(i32 %a) {
entry:
@@ -106,7 +121,9 @@ if.end:
}
; CHECK-LABEL: sltiu_beq1:
-; CHECK: sltu ${{[0-9]+}}
+; CHECK: sltu ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
define void @sltiu_beq1(i32 %a) {
entry:
@@ -122,8 +139,10 @@ if.end:
}
; CHECK-LABEL: sltiu_beq2:
-; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
-; CHECK: beqz $[[R0]]
+; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
+; MMR6: sltiu $[[R0:[0-9]+]], $4, -32768
+; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
+; CHECK: beqz $[[R0]]
define void @sltiu_beq2(i32 %a) {
entry:
@@ -139,7 +158,9 @@ if.end:
}
; CHECK-LABEL: sltiu_beq3:
-; CHECK: sltu ${{[0-9]+}}
+; CHECK: sltu ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}
+; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
define void @sltiu_beq3(i32 %a) {
entry:
Modified: llvm/trunk/test/CodeGen/Mips/seteq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/seteq.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/seteq.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/seteq.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@@ -13,9 +14,10 @@ entry:
%cmp = icmp eq i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
-; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
-; 16: move ${{[0-9]+}}, $24
+; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/seteqz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/seteqz.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/seteqz.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/seteqz.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 0, align 4
@j = global i32 99, align 4
@@ -11,14 +12,16 @@ entry:
%cmp = icmp eq i32 %0, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltiu ${{[0-9]+}}, 1
-; 16: move ${{[0-9]+}}, $24
+; 16: sltiu ${{[0-9]+}}, 1
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
%1 = load i32, i32* @j, align 4
%cmp1 = icmp eq i32 %1, 99
%conv2 = zext i1 %cmp1 to i32
store i32 %conv2, i32* @r2, align 4
-; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
-; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
-; 16: move ${{[0-9]+}}, $24
+; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/setge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setge.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setge.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setge.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -16,9 +17,10 @@ entry:
%cmp = icmp sge i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp sge i32 %0, %2
%conv2 = zext i1 %cmp1 to i32
Modified: llvm/trunk/test/CodeGen/Mips/setgek.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setgek.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setgek.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setgek.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@k = global i32 10, align 4
@r1 = common global i32 0, align 4
@@ -11,8 +12,9 @@ entry:
%cmp = icmp sgt i32 %0, -32769
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slti ${{[0-9]+}}, -32768
-; 16: move ${{[0-9]+}}, $24
-; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
+; 16: slti ${{[0-9]+}}, -32768
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
+; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/setle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setle.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setle.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setle.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -15,9 +16,10 @@ entry:
%cmp = icmp sle i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp sle i32 %2, %1
%conv2 = zext i1 %cmp1 to i32
Modified: llvm/trunk/test/CodeGen/Mips/setlt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setlt.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setlt.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setlt.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -15,7 +16,8 @@ entry:
%cmp = icmp slt i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move ${{[0-9]+}}, $24
+; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/setltk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setltk.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setltk.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setltk.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@@ -14,7 +15,8 @@ entry:
%cmp = icmp slt i32 %0, 10
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: slti $[[REGISTER:[0-9]+]], 10
-; 16: move $[[REGISTER]], $24
+; 16: slti $[[REGISTER:[0-9]+]], 10
+; MMR6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
+; 16: move $[[REGISTER]], $24
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/setne.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setne.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setne.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setne.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@@ -13,8 +14,9 @@ entry:
%cmp = icmp ne i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
-; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
-; 16: move ${{[0-9]+}}, $24
+; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
+; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
+; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/setuge.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setuge.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setuge.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setuge.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,9 +16,10 @@ entry:
%cmp = icmp uge i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp uge i32 %0, %2
%conv2 = zext i1 %cmp1 to i32
Modified: llvm/trunk/test/CodeGen/Mips/setugt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setugt.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setugt.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setugt.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,7 +16,8 @@ entry:
%cmp = icmp ugt i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move ${{[0-9]+}}, $24
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/setule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setule.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setule.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setule.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,9 +16,10 @@ entry:
%cmp = icmp ule i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move $[[REGISTER:[0-9]+]], $24
+; 16: xor $[[REGISTER]], ${{[0-9]+}}
%2 = load i32, i32* @m, align 4
%cmp1 = icmp ule i32 %2, %1
%conv2 = zext i1 %cmp1 to i32
Modified: llvm/trunk/test/CodeGen/Mips/setult.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setult.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setult.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setult.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -15,7 +16,8 @@ entry:
%cmp = icmp ult i32 %0, %1
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move ${{[0-9]+}}, $24
+; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: move ${{[0-9]+}}, $24
ret void
}
Modified: llvm/trunk/test/CodeGen/Mips/setultk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setultk.ll?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/setultk.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/setultk.ll Fri Jul 22 02:18:33 2016
@@ -1,4 +1,5 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
@@ -14,7 +15,8 @@ entry:
%cmp = icmp ult i32 %0, 10
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
-; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
-; 16: move ${{[0-9]+}}, $24
+; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
+; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16: move ${{[0-9]+}}, $24
ret void
}
Added: llvm/trunk/test/CodeGen/Mips/slt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/slt.ll?rev=276397&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/slt.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/slt.ll Fri Jul 22 02:18:33 2016
@@ -0,0 +1,18 @@
+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s
+
+define i32 @slt(i32 signext %a) nounwind readnone {
+ %1 = icmp slt i32 %a, 7
+ ; CHECK-LABEL: slt:
+ ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
+ %2 = select i1 %1, i32 3, i32 4
+ ret i32 %2
+}
+
+define i32 @sgt(i32 signext %a) {
+entry:
+ ; CHECK-LABEL: sgt:
+ %cmp = icmp sgt i32 %a, 32767
+ ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
+ %cond = select i1 %cmp, i32 7, i32 5
+ ret i32 %cond
+}
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Fri Jul 22 02:18:33 2016
@@ -270,6 +270,10 @@
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
+0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5
+0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256
+0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256
+0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x00 0x00 0x47 0x7c # CHECK: di
Modified: llvm/trunk/test/MC/Mips/micromips-el-fixup-data.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-el-fixup-data.s?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-el-fixup-data.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-el-fixup-data.s Fri Jul 22 02:18:33 2016
@@ -16,7 +16,7 @@ main:
addiu $sp, $sp, -16
bnez $9, lab1
-# CHECK: 09 b4 04 00 bne $9, $zero, 8
+# CHECK: 09 b4 04 00 bnez $9, 8
addu $zero, $zero, $zero
lab1:
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=276397&r1=276396&r2=276397&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Fri Jul 22 02:18:33 2016
@@ -288,6 +288,10 @@
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
+ slt $3, $4, $5 # CHECK: slt $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x50]
+ slti $3, $4, 256 # CHECK: slti $3, $4, 256 # encoding: [0x90,0x64,0x01,0x00]
+ sltiu $3, $4, 256 # CHECK: sltiu $3, $4, 256 # encoding: [0xb0,0x64,0x01,0x00]
+ sltu $3, $4, $5 # CHECK: sltu $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x90]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
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