[polly] r276247 - tests: fix order of memory accesses to ensure import succeeds

Tobias Grosser via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 21 00:12:17 PDT 2016


Author: grosser
Date: Thu Jul 21 02:12:17 2016
New Revision: 276247

URL: http://llvm.org/viewvc/llvm-project?rev=276247&view=rev
Log:
tests: fix order of memory accesses to ensure import succeeds

It seems the order in which we generated memory accesses changed such that
the import of these updated memory accesses failed for the 'loop3' statement
in this test case. Unfortunately, the existing CHECK lines were not strict
enough to catch this. Hence, besides fixing the order of the memory access
lines we also ensure that the memory access changes are both clearly visibly
and well checked.

Modified:
    polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions.ll
    polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop
    polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop.transformed

Modified: polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions.ll
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions.ll?rev=276247&r1=276246&r2=276247&view=diff
==============================================================================
--- polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions.ll (original)
+++ polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions.ll Thu Jul 21 02:12:17 2016
@@ -2,14 +2,22 @@
 ; RUN:                -polly-import-jscop-postfix=transformed -polly-codegen \
 ; RUN:                 < %s -S | FileCheck %s
 
-; CHECK: polly.stmt.loop2:
-; CHECK-NEXT:   %polly.access.A = getelementptr double, double* %A, i64 42
-; CHECK-NEXT:   %val_p_scalar_ = load double, double* %polly.access.A
+; CHECK-LABEL: polly.stmt.loop1:
+; CHECK-NEXT:   %3 = mul nsw i64 5, %polly.indvar
+; CHECK-NEXT:   %4 = sub nsw i64 %3, 10
+; CHECK-NEXT:   %polly.access.A = getelementptr double, double* %A, i64 %4
+; CHECK-NEXT:   store double 4.200000e+01, double* %polly.access.A, align 8
 
-; CHECK: polly.stmt.loop3:
+; CHECK-LABEL: polly.stmt.loop2:
+; CHECK-NEXT:   %polly.access.A10 = getelementptr double, double* %A, i64 42
+; CHECK-NEXT:   %val_p_scalar_ = load double, double* %polly.access.A10, align 8
+
+; CHECK-LABEL: polly.stmt.loop3:
 ; CHECK-NEXT:   %val.s2a.reload = load double, double* %val.s2a
-; CHECK-NEXT:   %scevgep[[R21:[0-9]*]] = getelementptr double, double* %scevgep{{[0-9]*}}, i64 %polly.indvar16
-; CHECK-NEXT:   store double %val.s2a.reload, double* %scevgep[[R21]]
+; CHECK-NEXT:   %7 = mul nsw i64 13, %polly.indvar16
+; CHECK-NEXT:   %8 = add nsw i64 %7, 5
+; CHECK-NEXT:   %polly.access.A20 = getelementptr double, double* %A, i64 %8
+; CHECK-NEXT:   store double %val.s2a.reload, double* %polly.access.A20, align 8,
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 

Modified: polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%25loop1---%25exit.jscop?rev=276247&r1=276246&r2=276247&view=diff
==============================================================================
--- polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop (original)
+++ polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop Thu Jul 21 02:12:17 2016
@@ -1,6 +1,6 @@
 {
-   "context" : "[arg] -> {  : arg >= -9223372036854775808 and arg <= 9223372036854775807 }",
-   "name" : "loop1 => exit",
+   "context" : "[arg] -> {  : -9223372036854775808 <= arg <= 9223372036854775807 }",
+   "name" : "%loop1---%exit",
    "statements" : [
       {
          "accesses" : [
@@ -9,7 +9,7 @@
                "relation" : "[arg] -> { Stmt_loop1[i0] -> MemRef_A[1 + i0] }"
             }
          ],
-         "domain" : "[arg] -> { Stmt_loop1[i0] : i0 >= 0 and i0 <= -2 + arg }",
+         "domain" : "[arg] -> { Stmt_loop1[i0] : 0 <= i0 <= -2 + arg }",
          "name" : "Stmt_loop1",
          "schedule" : "[arg] -> { Stmt_loop1[i0] -> [0, i0] }"
       },
@@ -24,22 +24,22 @@
                "relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_val[] }"
             }
          ],
-         "domain" : "[arg] -> { Stmt_loop2[i0] : i0 >= 0 and i0 <= -2 + arg }",
+         "domain" : "[arg] -> { Stmt_loop2[i0] : 0 <= i0 <= -2 + arg }",
          "name" : "Stmt_loop2",
          "schedule" : "[arg] -> { Stmt_loop2[i0] -> [1, i0] }"
       },
       {
          "accesses" : [
             {
-               "kind" : "read",
-               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }"
-            },
-            {
                "kind" : "write",
                "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_A[1 + i0] }"
+            },
+            {
+               "kind" : "read",
+               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }"
             }
          ],
-         "domain" : "[arg] -> { Stmt_loop3[i0] : i0 >= 0 and i0 <= -2 + arg }",
+         "domain" : "[arg] -> { Stmt_loop3[i0] : 0 <= i0 <= -2 + arg }",
          "name" : "Stmt_loop3",
          "schedule" : "[arg] -> { Stmt_loop3[i0] -> [2, i0] }"
       }

Modified: polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop.transformed
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%25loop1---%25exit.jscop.transformed?rev=276247&r1=276246&r2=276247&view=diff
==============================================================================
--- polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop.transformed (original)
+++ polly/trunk/test/Isl/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop.transformed Thu Jul 21 02:12:17 2016
@@ -6,7 +6,7 @@
          "accesses" : [
             {
                "kind" : "write",
-               "relation" : "[arg] -> { Stmt_loop1[i0] -> MemRef_A[1 + i0] }"
+               "relation" : "[arg] -> { Stmt_loop1[i0] -> MemRef_A[5 * i0 - 10]  }"
             }
          ],
          "domain" : "[arg] -> { Stmt_loop1[i0] : i0 >= 0 and i0 <= -2 + arg }",
@@ -31,12 +31,12 @@
       {
          "accesses" : [
             {
-               "kind" : "read",
-               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }"
+               "kind" : "write",
+               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_A[13 * i0 + 5] }"
             },
             {
-               "kind" : "write",
-               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_A[42] }"
+               "kind" : "read",
+               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }"
             }
          ],
          "domain" : "[arg] -> { Stmt_loop3[i0] : i0 >= 0 and i0 <= -2 + arg }",




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