[PATCH] D22595: [tsan] Enable 48-bit VMA support on aarch64

[Adhemerval Zanella via llvm-commits]

zatrazz created this revision.
zatrazz added reviewers: kcc, pcc, eugenis, samsonov, rengolin, aizatsky.
zatrazz added a subscriber: llvm-commits.
zatrazz added a project: Sanitizers.
Herald added subscribers: kubabrecka, rengolin, aemerson.

This patch adds 48-bits VMA support for tsan on aarch64.  As current
mappings for aarch64, 48-bit VMA also supports PIE executable.  This
limits the mapping mechanism because the PIE address bits
(usually 0aaaaXXXXXXXX) makes it harder to create a mask/xor value
to include all memory regions.  I think it is possible to create a
large application VAM range by either dropping PIE support or tune
current range.

The patch also remove the heap accounting and checking if the architecture
does not uses 64-bit size allocator.  This is due the fact heap VAM
range is used only for the allocator on TSAN, so this allows use the
range for application usage.

It also changes slight the way addresses are packed in SyncVar structure:
previously it assumes x86_64 as the maximum VMA range.  Since ID is 14 bits
wide, shifting 48 bits should be ok.

Tested on x86_64, ppc64le and aarch64 (39 and 48 bits VMA).

https://reviews.llvm.org/D22595

Files:
  lib/tsan/rtl/tsan_platform.h
  lib/tsan/rtl/tsan_platform_linux.cc
  lib/tsan/rtl/tsan_platform_posix.cc
  lib/tsan/rtl/tsan_sync.h

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D22595.64764.patch
Type: text/x-patch
Size: 9670 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160720/fda5eaf0/attachment.bin>