[PATCH] D22580: Fix bug in clearance calculation

[Marina Yatsina via llvm-commits]

myatsina created this revision.
myatsina added a reviewer: mkuper.
myatsina added a subscriber: llvm-commits.

The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.


https://reviews.llvm.org/D22580

Files:
  lib/CodeGen/ExecutionDepsFix.cpp
  test/CodeGen/X86/break-false-dep.ll

Index: lib/CodeGen/ExecutionDepsFix.cpp
===================================================================
--- lib/CodeGen/ExecutionDepsFix.cpp
+++ lib/CodeGen/ExecutionDepsFix.cpp
@@ -520,8 +520,6 @@
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg())
       continue;
-    if (MO.isImplicit())
-      break;
     if (MO.isUse())
       continue;
     for (int rx : regIndices(MO.getReg())) {
Index: test/CodeGen/X86/break-false-dep.ll
===================================================================
--- test/CodeGen/X86/break-false-dep.ll
+++ test/CodeGen/X86/break-false-dep.ll
@@ -199,3 +199,13 @@
 ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
 ;AVX-NEXT: vmovsd [[XMM0]],
 }
+
+define double @inlineasmdep(i64 %arg) {
+top:
+  tail call void asm sideeffect "", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
+  %tmp1 = sitofp i64 %arg to double
+  ret double %tmp1
+;AVX-LABEL:@inlineasmdep
+;AVX: vxorps  [[XMM0:%xmm[0-9]+]], [[XMM0]], [[XMM0]]
+;AVX-NEXT: vcvtsi2sdq {{.*}}, [[XMM0]], {{%xmm[0-9]+}}
+}


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D22580.64727.patch
Type: text/x-patch
Size: 1023 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160720/8f5834c7/attachment.bin>