[PATCH] D22520: [mips] zeroext and logical 'and' mask optimizations

[Simon Dardis via llvm-commits]

sdardis created this revision.
sdardis added reviewers: dsanders, vkalintiris.
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sdardis set the repository for this revision to rL LLVM.
Herald added subscribers: sdardis, dsanders.

This patch teaches the MIPS backend to use shifts and bitwise extract and 
inserts when a solid mask of the form 0...1 or 1...0 rather than synthesising
the corresponding mask into a register and performing a logical and.

For MIPSR2, (d)ins(u) and (d)ext along with the zero register can be used to
implement masking operations that would be use logical and with a large
constant.

This reduces all such masking operations to a maximum of 2 instructions (shift
left+shift right or vice versa) or a minimum of one (bitwise extract or bitwise
insert with zero) in some cases.

As part of this, use the same trick to optimize zeroext for MIPS64R2.

Repository:
  rL LLVM

https://reviews.llvm.org/D22520

Files:
  lib/Target/Mips/Mips64InstrInfo.td
  lib/Target/Mips/MipsInstrInfo.td
  lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  test/CodeGen/Mips/cconv/arguments-varargs.ll
  test/CodeGen/Mips/fcopysign-f32-f64.ll
  test/CodeGen/Mips/fcopysign.ll
  test/CodeGen/Mips/llvm-ir/and-opts.ll
  test/CodeGen/Mips/llvm-ir/and.ll
  test/CodeGen/Mips/llvm-ir/zext.ll
  test/CodeGen/Mips/load-store-left-right.ll
  test/CodeGen/Mips/mips64-f128.ll
  test/CodeGen/Mips/o32_cc_vararg.ll
  test/MC/Mips/sext_64_32.ll

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