[PATCH] D22511: [InstCombine] Enable cast-folding in logic(cast(icmp), cast(icmp))

[David Majnemer via llvm-commits]

majnemer added a subscriber: majnemer.
majnemer accepted this revision.
majnemer added a reviewer: majnemer.
majnemer added a comment.
This revision is now accepted and ready to land.

LGTM with nits addressed.


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Comment at: test/Transforms/InstCombine/zext.ll:78-82
@@ +77,7 @@
+; CHECK-LABEL: @fold_logic_zext_icmp(
+; CHECK-NEXT:    %1 = icmp sgt i64 %a, %b
+; CHECK-NEXT:    %2 = icmp slt i64 %a, %c
+; CHECK-NEXT:    %3 = and i1 %1, %2
+; CHECK-NEXT:    %4 = zext i1 %3 to i8
+; CHECK-NEXT:    ret i8 %4
+define i8 @fold_logic_zext_icmp(i64 %a, i64 %b, i64 %c) {
----------------
I'd recommend pattern matching these similar to the test above.

================
Comment at: test/Transforms/InstCombine/zext.ll:94-101
@@ +93,10 @@
+; nested logical operators.
+; CHECK-LABEL: @fold_nested_logic_zext_icmp(
+; CHECK-NEXT:    %1 = icmp sgt i64 %a, %b
+; CHECK-NEXT:    %2 = icmp slt i64 %a, %c
+; CHECK-NEXT:    %3 = and i1 %1, %2
+; CHECK-NEXT:    %4 = icmp eq i64 %a, %d
+; CHECK-NEXT:    %5 = or i1 %3, %4
+; CHECK-NEXT:    %6 = zext i1 %5 to i8
+; CHECK-NEXT:    ret i8 %6
+define i8 @fold_nested_logic_zext_icmp(i64 %a, i64 %b, i64 %c, i64 %d) {
----------------
Ditto.


https://reviews.llvm.org/D22511