[PATCH] D18916: AMDGPU/SI: Fix regclass for the pseudo sgpr spill instructions

[Matt Arsenault via llvm-commits]

arsenm added a comment.

ping, I just ran into this.

The test can also probably be reduced with inlineasm


================
Comment at: test/CodeGen/AMDGPU/sgpr-spill-regclass.ll:10
@@ +9,3 @@
+bb:
+  %tmp = tail call i32 @llvm.r600.read.tidig.z() #2
+  %tmp3 = zext i32 %tmp to i64
----------------
needs update


https://reviews.llvm.org/D18916