[PATCH] D20474: when calculating RegUsages, ignore instructions which are uniformed after vectorization

[Wei Mi via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL275912: Use uniforms set to populate VecValuesToIgnore. (authored by wmi).

Changed prior to commit:
  https://reviews.llvm.org/D20474?vs=64343&id=64380#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D20474

Files:
  llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/trunk/test/Transforms/LoopVectorize/PowerPC/vsx-tsvc-s173.ll
  llvm/trunk/test/Transforms/LoopVectorize/X86/avx512.ll
  llvm/trunk/test/Transforms/LoopVectorize/X86/reg-usage.ll
  llvm/trunk/test/Transforms/LoopVectorize/reverse_induction.ll

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