[llvm] r275824 - [Hexagon] Revert r275822: mistake in commit message

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Mon Jul 18 12:34:49 2016
New Revision: 275824

URL: http://llvm.org/viewvc/llvm-project?rev=275824&view=rev
Log:
[Hexagon] Revert r275822: mistake in commit message

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=275824&r1=275823&r2=275824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Mon Jul 18 12:34:49 2016
@@ -447,13 +447,7 @@ static bool RetCC_Hexagon32(unsigned Val
                             MVT LocVT, CCValAssign::LocInfo LocInfo,
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
   if (LocVT == MVT::i32 || LocVT == MVT::f32) {
-    // Note that use of registers beyond R1 is not ABI compliant. However there
-    // are (experimental) IR passes which generate internal functions that
-    // return structs using these additional registers.
-    static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
-                                        Hexagon::R2, Hexagon::R3,
-                                        Hexagon::R4, Hexagon::R5};
-    if (unsigned Reg = State.AllocateReg(RegList)) {
+    if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }