[PATCH] D22354: AVX-512: Fixed BT instruction selection on AVX-512

[Elena Demikhovsky via llvm-commits]

delena marked 2 inline comments as done.
delena added a comment.

Sanjay, thanks a lot for the review. I'm uploading a new patch.


================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:15072-15091
@@ +15071,22 @@
+
+  // If LHS is i8, promote it to i32 with any_extend.  There is no i8 BT
+  // instruction.  Since the shift amount is in-range-or-undefined, we know
+  // that doing a bittest on the i32 value is ok.  We extend to i32 because
+  // the encoding for the i16 version is larger than the i32 version.
+  // Also promote i16 to i32 for performance / code size reason.
+  if (LHS.getValueType() == MVT::i8 ||
+      LHS.getValueType() == MVT::i16)
+      LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
+
+  // If the operand types disagree, extend the shift amount to match.  Since
+  // BT ignores high bits (like shifts) we can use anyextend.
+  if (LHS.getValueType() != RHS.getValueType())
+    RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
+
+  SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
+  X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
+  return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
+                     DAG.getConstant(Cond, dl, MVT::i8), BT);
+}
+
+/// Result of 'and' or 'trunc to i1' is compared against zero.
----------------
spatel wrote:
> This is all copied code & comments; please add a helper function instead of duplicating. That should make it easier to read too.
I'll upload the updated patch.


Repository:
  rL LLVM

https://reviews.llvm.org/D22354